Method for forming submicron bipolar transistors without epitaxi

Details Method for forming submicron bipolar transistors without epitaxi Method for forming submicron bipolar transistors without epitaxi

1981-10-22

1984-09-25

Hearn, Brian E.

Metal working

Method of mechanical manufacture

Assembling or joining

29571, 29578, 29576W, 148 15, 148188, 148191, 357 34, 357 47, 357 56, 357 52, 357 50, H01L 21265, H01L 2176

Patent

active

044728735

ABSTRACT:
A vertical bipolar transistor is fabricated in a semiconductor substrate without an epitaxial layer using oxide isolation and ion implantation techniques. Ion implantation energies in the KEV ranges are used to implant selected ions into the substrate to form a collector region and buried collector layer less than 1 micron from the surface of the device, and then to form a base region of opposite conductivity type in the collector layer and an emitter region of the first conductivity type in the base region. Even though ion implantation techniques are used to form all regions, the base and the emitter regions can, if desired, be formed to abut the field oxide used to laterally define the islands of semiconductor material. The field oxide is formed to a thickness of less than 1 micron and typically to a thickness of approximately 0.4 microns, thereby substantially reducing the lateral oxidation of the semiconductor silicon islands and making possible devices of extremely small size, typically around 16-18 square microns. During the implantation of channel stop regions between the islands of semiconductor material a thin oxide layer is used to screen the underlying silicon from forming oxidation-induced stacking faults by the subsequent high dose field implantation and oxidation. A nitrogen anneal following this implantation and prior to forming the field oxide further reduces the frequency of stacking faults.

REFERENCES:
patent: 4111720 (1978-09-01), Michel et al.
patent: 4140558 (1979-02-01), Murphy et al.
patent: 4240092 (1980-12-01), Kuo

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