Method for forming studs and interconnects in a multi-layered se

Details Method for forming studs and interconnects in a multi-layered se Method for forming studs and interconnects in a multi-layered se

1996-12-18

1997-11-18

Meier, Stephen

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Of specified configuration

257751, 257725, H01L 2348, H01L 2352, H01L 2940

Patent

active

056891407

ABSTRACT:
A method of manufacturing a semiconductor device having a stud and interconnect in a dual damascene structure uses selective deposition. The method includes forming a trench including a first opening portion and a second opening portion in a dielectric layer, forming a first adhesion layer on a surface exposed by the first opening portion, forming a second adhesion layer on a surface exposed by the second opening portion, and selectively depositing a conductive material on the first adhesion layer and the second adhesion layer, wherein growth of the conductive material on the second adhesion layer starts after growth of the conductive material on the first adhesion layer has started. The first and second adhesion layers are of different materials.

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