Method for forming structures on a wafer

Details Method for forming structures on a wafer Method for forming structures on a wafer

2001-09-14

2003-01-21

Nelms, David (Department: 2818)

Semiconductor device manufacturing: process

Packaging or treatment of packaged semiconductor

Insulative housing or support

Reexamination Certificate

active

06509208

ABSTRACT:

TECHNICAL FIELD
This invention relates to fabricating structures on wafers.
BACKGROUND
With wafer level packaging (WLP), semiconductor manufacturing processes test and burn-in integrated circuits (ICs) at a wafer level instead of testing and burning-in the ICs in individual packaged form. Such wafer level test (WLT) and wafer level burn-in (WLBI) require placing the wafers on test boards. Compliant structures are used to reduce thermal and mechanical stresses between the wafer and the test board and to assist in providing electrical interconnects so that the ICs can be tested while in wafer form. Since compliant structures are elastic, they can be moved in up to three-dimensions. In other words, in a raised temperature environment, compliant structures decouple the stress when a wafer and a test board expand at different rates due to the different coefficients of thermal expansion between the test board and the wafer.
Several methods of manufacturing compliant structures exist. One method includes forming compliant structures by wire bonding springs onto the surface of the wafer and plating the wire bond spring structures using an alloy. Another compliant structure manufacturing process includes laminating a polymer on the top of the wafer, embossing a negative shape of the springs into the polymer to form a mold, and then plating an alloy into the embossed mold.
SUMMARY
The invention is directed to a method for fabricating structures on an integrated circuit wafer. In particular, the invention relates to forming compliant elements on the surface of a wafer by forming the compliant element in a mold prior to placing the compliant element on the wafer. One practice of the invention includes applying an anti-sticking coating to a surface of a mold, depositing a first material on the anti-sticking coating, and removing a portion of the first material to expose the anti-sticking coating. The resulting first interface between the mold and the first material has a first adhesiveness.
The method also includes placing the anti-sticking coating in contact with the wafer, and removing the mold from the wafer. This forms a second interface between the material and the wafer that has a second adhesiveness greater than the first adhesiveness.
One aspect further includes applying a second material to the wafer and to the first material. This second material forms a rerouting layer. In addition, the first material is laminated onto the wafer. Further, laminating the first material to the wafer also includes spraying a solvent onto the surface of the substrate.
In other embodiments, the first material can also form a rerouting layer, a snap mechanism, a compression stop and/or a compliant structure. In other embodiments, the first material can be removed leaving the second material as the compliant structure.
This method can be performed at low temperatures, thereby preventing damage to the ICs on the wafer from mechanical stress. In addition, the method allows uniform deposition of a variety of materials (e.g., polymethyl methacrylate, silicone, polymers, and epoxies) on the wafer. Complicated three-dimensional shapes can also be created to connect the wafer to a test board (e.g., a snap mechanism).


REFERENCES:
patent: 5468995 (1995-11-01), Higgins, III
patent: 5961217 (1999-10-01), Heshmat
patent: 6245595 (2001-06-01), Nguyen et al.
patent: 6313528 (2001-11-01), Solberg

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