Semiconductor device manufacturing: process – Chemical etching – Combined with the removal of material by nonchemical means
Reexamination Certificate
2001-03-30
2002-09-24
Powell, William A. (Department: 1765)
Semiconductor device manufacturing: process
Chemical etching
Combined with the removal of material by nonchemical means
C216S038000, C216S079000, C216S099000, C257S368000, C257S632000, C257S649000, C438S724000, C438S744000, C438S745000, C438S757000
Reexamination Certificate
active
06455433
ABSTRACT:
FIELD OF THE INVENTION
The present invention generally relates to a method for forming sidewall spacers for insulating polysilicon gates and devices formed and more particularly, relates to a method for forming dielectric sidewall spacers with square shoulders on polycide gates for eliminating electrical shorting problems between the polysilicon gate and source/drain silicide in the semiconductor structure and devices fabricated by the method.
BACKGROUND OF THE INVENTION
Modern semiconductor devices are built on semi-conducting substrates such as silicon substrates that have P
+
and N
+
type doped regions in the substrates as basic elements of the device. These doped regions must be connected in a specific configuration to form a desired circuit. The circuit needs to be accessible to the outside world through conducting pads for testing and through bonding into a packaged chip. To form a semiconductor circuit, at least one layer of a conducting material such as metal must be deposited and patterned to form contacts and interconnects between the different regions of the chip. For instance, in a typical semiconductor fabrication process, a silicon wafer is first covered with an insulating layer and then, patterned and etched for contact openings in the insulating layer. A conductive material is then deposited and defined to form contact plugs and interconnecting leads.
On top of the silicon wafer, semiconductor gates are normally formed of a polysilicon material with a thin gate oxide layer formed in-between the polysilicon gate and the silicon substrate. A typical semiconductor gate structure
10
is shown in
FIGS. 1A and 1B
. In order to insulate the polysilicon gate
12
, a silicon oxide layer
14
or any other dielectric material layer such as silicon nitride or silicon oxynitride can also be used. A thick silicon oxide layer of several thousand angstrom thickness can be deposited by a rapid thermal chemical vapor deposition (RTCVD) technique. In the process of forming such sidewall spacers
16
from the dielectric layer
14
, it is important that the material deposited, i.e. silicon oxide, must have both a high deposition rate such that a thick layer can be deposited in a short period of time and also a good conformability such that the polysilicon gate can be completely covered. For instance, when silicon oxide is deposited, the TEOS (tetra-ethoxy-silane) chemistry can be used at a high deposition temperature of 800° C. for achieving a deposition rate of about 1000 Å/min. Such a high deposition rate would satisfy a throughput requirement for the semiconductor device. The high deposition temperature limits such deposition process to the front end of the fabrication process wherein metal wiring layers are not involved.
After the conformal deposition of the silicon oxide layer
14
to approximately 5000~8000 Å thickness, a reactive ion etching (RIE) method is conventionally used to pattern the gate sidewall spacers
16
. The RIE technique is chosen since the anisotropic plasma used in the technique is effective in forming the sidewall spacers
16
on the gate
12
. In the RIE technique, positive plasma ions in a parallel-plate RF reactor are used to provide a source of energetic particle bombardment for the etched surface, producing vertical edges in the etched film with negligible undercutting. The ion bombardment increases the reaction rate of spontaneously occurring processes and prompts reactions which do not occur without radiation. In a typical reactive ion etching system, the wafers are placed on the powered electrode of a parallel-plate RF reactor wherein horizontal surfaces are subjected to both reactant species and impinging ions, while vertical sidewalls are only subjected to reactive species.
In the conventional method of patterning sidewall spacers by the reactive ion etching method, it has been discovered that the plasma ions bombarded during the etching process damage the silicon surface at the source/drain area that will enhance dark current (or leakage current) and impact the signal
oise ratio of a photoelectronic device. As shown in
FIG. 1B
, a surface layer
18
of the silicon substrate
20
in the source/drain area
22
,
24
is it frequently damaged by the plasma ions and severely effects the reliability of the device fabricated.
A method for fabricating a conventional sidewall spacer on a polysilicon gate structure is shown in FIGS.
1
A~
1
E.
FIGS. 1A and 1B
show a polysilicon gate formation and LDD implant, respectively. For instance, in
FIG. 1A
, the semiconductor structure
10
is first formed on a silicon substrate
12
a thin gate oxide layer
14
having a thickness of less than 200 Å. Birds beak isolation
16
of silicon oxide are also formed for isolation of devices. On top of the gate oxide layer
14
, is then deposited a doped polysilicon layer
18
and a TiN layer
20
, sequentially. The semiconductor structure
10
is then patterned and a polysilicon gate
22
with a titanium silicide layer
24
on top is then formed insulated by sidewall spacers
26
formed of a dielectric material of either SiO
2
or Si
3
N
4
. This is shown in FIG.
1
B. The LDD (lightly doped drain) implantation is performed in the source/drain regions
28
,
30
.
In the next step of the process, a cobalt layer
32
is blanket deposited on top of the semiconductor structure
10
by a technique such as sputtering. This is shown in FIG.
1
C. The cobalt layer
32
and the silicon substrate
12
then reacts when annealed at a high temperature to form source/drain silicide layers
34
,
36
of cobalt silicide, as shown in FIG.
1
D. The unreacted cobalt layer
32
is then removed in a wet etch process with titanium silicide layer
24
remaining on the polysilicon gate
22
. This is shown in FIG.
1
E.
As shown in FIGS.
1
A~
1
E, the most frequently used metal silicide material is TiSi
2
, however, other metal silicides such as CoSi
2
and NiSi
2
have also been used in forming polycide gates. The titanium silicide layer is normally formed by a two-stage annealing method. A thin layer of titanium is first sputtered or deposited by a chemical vapor deposition technique, or a titanium/silicon layer can be deposited by a co-sputtering technique. A first stage annealing process is then conducted at about 650° C. such that titanium metal reacts with silicon substrate that it contacts to form titanium silicide. At this stage, the titanium silicide formed is the higher resistance value C49 phase. The unreacted titanium metal is then removed by a basic solution such as a solution of 5:1:1 DiW, 30% H
2
O
2
, NH
4
OH. During the same etching process, the silicon oxide surface layer formed is also removed. The semiconductor structure is then annealed in a second stage at 800° C. in a nitrogen containing gas. During the second stage annealing, the titanium silicide of higher resistance value C49 phase is transformed to a lower resistance value C54 phase such that the lowest sheet resistance can be achieved.
In the conventional sidewall spacers
26
shown in
FIG. 1E
, the thickness is limited such that electrical shorting between the polysilicon gate
22
and the source/drain silicide
34
,
36
frequently occurs. Such electrical shorting can cause serious damages to the semiconductor structure and thus greatly reduces its reliability.
It is therefore an object of the present invention to provide a method for forming sidewall spacers on a polysilicon gate without the drawbacks or shortcomings of the conventional method.
It is another object of the present invention to provide a method for forming sidewall spacers on a polysilicon gate wherein the spacers do not have a tapered shoulder region.
It is a further object of the present invention to provide a method for forming sidewall spacers on a polysilicon gate wherein the spacers are equipped with square shoulders.
It is another further object of the present invention to provide a method for forming sidewall spacers with square shoulders such that the possibility of electrical shorting between the poly
Chang Yao-Chi
Lu Kao-Ming
Powell William A.
Taiwan Semiconductor Manufacturing Co. Ltd.
Tung & Associates
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