Method for forming solder joints for a flip chip assembly

Semiconductor device manufacturing: process – Bonding of plural semiconductor substrates

Reexamination Certificate

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C438S106000, C438S107000, C438S108000, C257S772000, C257SE23023, C257SE23026, C257SE21508

Reexamination Certificate

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07601612

ABSTRACT:
A method for forming a solder joint for a package arrangement with a dispersed Sn microstructure provides a flip chip on a package, with a flip chip having solder bumps to be connected by eutectic solder joints to pads on the package. The eutectic solder is reflowed at a solder bump/pad interface with a eutectic reflow profile that is configured to achieve eutectic solder joints having substantially evenly distributed Sn grains. The eutectic reflow profile includes an increased cooling rate and decreased hold time with a higher peak temperature. A defined ratio of the pad openings in the solder mask to the under bump metallurgy is provided. The eutectic reflow profile and the defined ratio prolong fatigue life in the package arrangement.

REFERENCES:
patent: 5202153 (1993-04-01), Siuta
patent: 6229207 (2001-05-01), Master
patent: 6617195 (2003-09-01), Master et al.
patent: 2003/0186072 (2003-10-01), Soga et al.
Wu et al., “A study of flip-chip UBM/bump reliability with effects of SnPb solder composition,” Mar. 2005, Microelectronics Reliability 46, pp. 41-52.
Rinne, “Issues in accelerated electromigration of solder bumps,” Sep. 2003, Microelectronics Reliability 43, pp. 1975-1980.

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