Method for forming silicon film with changing grain size by...

Details Method for forming silicon film with changing grain size by... Method for forming silicon film with changing grain size by...

2005-03-29

2005-03-29

Tran, Michael (Department: 2818)

Active solid-state devices (e.g., transistors, solid-state diode

Non-single crystal, or recrystallized, semiconductor...

Amorphous semiconductor material

C257S002000, C257S003000, C257S004000, C257S005000, C257S055000, C257S063000, C257S315000, C438S482000, C438S488000, C438S674000, C438S764000

Reexamination Certificate

active

06872972

ABSTRACT:
Roughly described, a silicon layer transitions from polysilicon at one surface to amorphous silicon at the opposite surface. The transition can be monotonic, and can be either continuous or it can change abruptly from polysilicon to amorphous silicon. If such a layer is formed as the floating gate of a floating gate transistor structure, the larger grain structure adjacent to the tunnel dielectric layer reduces the formation of a tip (protrusion) and thus reduces leakage. On the other hand, the smaller grain structure adjacent to the gate dielectric layer produces a smooth, more uniform gate dielectric layer. The polysilicon-to-amorphous silicon transistor can be fabricated with a temperature profile that favors polysilicon formation at the start of floating gate deposition, and transitions during deposition to a temperature that favors amorphous silicon deposition at the end of floating gate deposition.

REFERENCES:
patent: 4748133 (1988-05-01), Griswold
patent: 4945393 (1990-07-01), Beltram et al.
patent: 4963506 (1990-10-01), Liaw et al.
patent: 5017308 (1991-05-01), Iijima
patent: 5017980 (1991-05-01), Gill et al.
patent: 5147813 (1992-09-01), Woo
patent: 5445982 (1995-08-01), Hwang
patent: 5711998 (1998-01-01), Shufflebotham
patent: 5751637 (1998-05-01), Chen et al.
patent: 5753134 (1998-05-01), Biebl
patent: 5863706 (1999-01-01), Komatsu et al.
patent: 5874129 (1999-02-01), Beinglass et al.
patent: 5972765 (1999-10-01), Clark et al.
patent: 6013551 (2000-01-01), Chen et al.
patent: 6023093 (2000-02-01), Gregor et al.
patent: 6114722 (2000-09-01), Jan et al.
patent: 6143632 (2000-11-01), Ishida et al.
patent: 6218246 (2001-04-01), Xiang et al.
patent: 6221705 (2001-04-01), Rost et al.
patent: 6268068 (2001-07-01), Heuer et al.
patent: 6268086 (2001-07-01), Honbo et al.
patent: 6326274 (2001-12-01), Rost et al.
patent: 6373092 (2002-04-01), Okumoto
patent: 6670241 (2003-12-01), Kamal et al.
patent: 20040077155 (2004-04-01), Chen et al.
Kwon, Hyungshin et al., “Electrical Characteristics of Ultrathin Gate Oxide Prepared by Postoxidation Annealing in ND3,” Applied Physics Letters, 76 (6): 772-773 (Feb. 7, 2000).
U.S. Appl. No. 10/180,168, filed Jun. 26, 2002, Luoh.
Kahler, U., et al. “Size related properties of silicon nanoparticles from decomposition of SiOx” http://www.mpi-halle.mpg.de/annual_reports/2000.pdf/jb_results_14.pdf, 2 pages.
“Polysilicon: The Successor Technology,” http://www.wtec.org/loyola/dsply_jp/c5_s5.htm (June 1992), 3 pages.
Polysilicon TFT, The Future is clear with Toshiba, http://www.toshiba-europe.com/computers/tnt/tft/ (2002), 1 page.
Higher Resolution, The Future is clear with Toshiba, http://www.toshiba-europe.com/computers/tnt/tft/resolution.htm (2002), 1 page.
Polysilicon Explained, The Future is clear with Toshiba, http://www.toshiba-europe.com/computers/tnt/tft/explained.htm (2002), 1 page.
“Flash Memory Technology” Chapter 10, Integrated Circuit Engineering Corporation, http://smithsonianchips.si.edu/ice/cd/MEMORY97/SEC10.PDF (1997), pp. 10-1 through 10-16.
Wilson, Ron, “Flash gets a quantum makeover at IEDM,” EETIMES (Dec. 13, 2002), 4 pages.
“The K-Input Floating-Gate MOS (FGMOS) Transistor” http://people.ece.cornell.edu/minch/talks/FGMOSTdevicelayout.pdf, 22 pages.
Dipert, Brian, “Exotic Memories, diverse approaches” www.ednmag.com (Apr. 26, 2001), 9 pages.
Lammers, David, “Chip makers bang away at metal gates” EETIMES (Nov. 26, 2002), 3 pages.
“Characterizing Very Thin ONO Gates with Laser Spectroscopic Ellipsometry” Rudolph Technologies, Inc. Application Reports (2001) http://www.rudolphtech.com/reports/VeryThinONOGates.htm, 3 pages.
Dorsch, Jeff, “Applied Debuts RTP System, Company also adds CMP Process, defect detection system” Electronic News (Sep. 20, 1999), 3 pages.

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