Method for forming SiGe bipolar transistor

Details Method for forming SiGe bipolar transistor Method for forming SiGe bipolar transistor

2000-04-12

2001-12-25

Smith, Matthew (Department: 2825)

Semiconductor device manufacturing: process

Forming bipolar transistor by formation or alteration of...

C438S341000, C438S353000, C438S359000, C438S361000

Reexamination Certificate

active

06333235

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method of forming a SiGe bipolar transistor, and especially relates to a method for forming a SiGe bipolar transistor utilized in a high frequency circuit with lowered thermal budget.
2. Description of the Prior Art
Because of the characteristic of the bipolar transistor, and because the signal processed by the transistor in the radio frequency circuit is a signal having high frequency, the bipolar transistor, especially the SiGe bipolar transistor, is frequently employed in the radio frequency circuit. However the traditional SiGe bipolar transistor manufacturing process has many disadvantages such as low yield resulting from the low growth rate of the epitaxial growth process. In addition, in the traditional method, the epitaxial growth process is utilized two times when fabricating the SiGe bipolar transistor. The first epitaxial growth process is used to fabricate the collector layer, which is about 1 micron in thickness, and the second epitaxial growth process is used to form the epitaxial bass layer. Because the epitaxial growth process takes a lot of time, thus the two epitaxial growth processes utilized by the traditional SiGe bipolar transistor manufacturing process take much more time, and take longer cycling time as well as producing lower yield.
In addition, before epitaxially growing the SiGe layer, it is necessary to proceed with the wafer, which is very troublesome. Also, this tends to waste manufacturing time and result in lower yield to some extent. The process sequence employed to manufacture the heterojunction bipolar transistor (HBT) is described to illustrate how a SiGe bipolar transistor is fabricated via the traditional process.
As shown in
FIG. 1A
, the first step is to form a P type epitaxial layer
10
on a silicon substrate
11
, and the next step is to form a n
+
buried layer
12
on the P type epitaxial layer
10
by an implanting step. Followed by the foregoing implanting step, a n
−
epitaxial layer
14
is formed on the n
+
buried layer
12
by a first expitaxial growth step, which is controlled at a temperature from about 1000 C. to 1200 C. Subsequently a first photography step and a first etching step are used to etch the n
−
epitaxial layer
14
and then the trench in the n
+
buried layer
12
and the P type epitaxial layer
10
is defined, exposing a portion of the silicon substrate
11
. The concentration of the conductive carrier in the n
−
epitaxial layer
14
is designed to be that of the collector of the SiGe bipolar transistor. The etched n
−
epitaxial layer
14
includes the first area
14
a
having a first cave and the second area
14
b
having a second cave.
The first area
14
a
is designed to be defined as the active area of the transistor that will be fabricated in the following processes, and the second area
14
b
is designed to be defined as the collector of the transistor that will be fabricated in the following processes. The next step is to form the trench isolation
16
, which comprised of polysilicon portion
16
a
and oxide portion
16
b
at the interior surface of the trench at the bottom of both the first cave and the second cave. The silicon dioxide is then filled into the first cave in the etched portion of the n
−
epitaxial layer
14
, so the first silicon dioxide pattern
18
a
is formed in the first area
14
a
of the n
−
epitaxial layer
14
. In addition, the second silicon dioxide pattern
18
b
is formed in the second area
14
b
of the n
−
epitaxial layer
14
.
After the active area and collector of the transistor have been defined, the base of the transistor is to be defined according to the following processes. However, a layer of native oxide is always expectedly formed on the surface of the first area
14
a
and the second area
14
b
of the n
−
epitaxial layer
14
. Due to the unavoidable formation of the native oxide layer
22
on the n
−
epitaxial layer
14
, referring to
FIG. 1B
, the first polysilicon layer
25
is formed on the native oxide layer
22
. The wafer having the native oxide layer
22
on the second area
14
b
of the n
−
epitaxial layer
14
is immersed into HF to remove the exposed native oxide layer. It is important that the wafer must be directly sent to the tube which growing the GeSi epitaxial layer
30
(referring to
FIG. 1C
) without any cleaning step using water. The transmission of the wafer which was immersed into the HF is very dangerous for the operator, and a layer of several angstroms of native oxide layer
22
on the surface of the first area
14
a
of the n
−
epitaxial layer
14
still exist after the etching process using HF. Though the residual native oxide layer
22
is not shown in FIG.
1
B and
FIG. 1C
, it still exists between the GeSi epitaxial layer
30
and the first area
14
a
of the n
−
epitaxial layer
14
. So the yield of fabricating SiGe bipolar transistor using prior art is relatively lowered, and the cycling time is increased because the GeSi epitaxial layer
30
is formed by a second epitaxial growth process controlled under about 550 degrees in the centigrade scale.
The GeSi epitaxial layer
30
mentioned above is designed as the base of the SiGe bipolar transistor that is to be fabricated in the following processes, in addition, the SiGe bipolar transistor is usually employed in the high frequency circuit. So the concentration of the carrier and the thickness of the base of the SiGe bipolar transistor must be very carefully controlled.
After the GeSi epitaxial layer
30
had been formed on the surface of the second area
14
b
of the n
−
epitaxial layer
14
, the first polysilicon layer
25
is transferred into the polycrystalline GeSi layer
35
. Next, and referring to
FIG. 1D
, a first silicon nitride layer
38
and a second polysilicon layer
40
are subsequently formed on the GeSi epitaxial layer
30
and the polycrystalline GeSi layer
35
. In order to define the base of the transistor, a second silicon nitride layer
42
and a silicon dioxide layer
44
are subsequently formed on the second polysilicon layer
40
followed by their being patterning. So the patterned second silicon nitride layer
42
and the patterned silicon dioxide layer
44
are formed on the surface of the second polysilicon layer
40
in the first area
14
a.
Then an implantation step is utilized to form the P
+
region, besides, an oxidation step is utilized to proceed with the wafer, so the portion of the second polysilicon layer
40
without coverage from the patterned second silicon nitride layer
42
are transformed to the third silicon dioxide layer
46
as shown in FIG.
1
E. In addition, the P
+
region is driven deeper into the n
−
epitaxial layer
14
. Subsequently, as shown in
FIG. 1E
, the patterned second silicon dioxide layer
44
is removed and the patterned second silicon nitride layer
42
is exposed. This is followed by etching the patterned second silicon nitride layer
42
, a portion of the first silicon nitride layer
38
is covered by the remaining second polysilicon layer
40
and the remaining second polysilicon layer
40
are removed, as shown in
FIG. 1F
, and a portion of the GeSi epitaxial layer
30
is exposed.
These steps are followed by subsequently forming a n
+
polysilicon layer
50
and a third silicon nitride layer
52
on the exposed portion of GeSi epitaxial layer
30
, a photolithography step and an etching step are employed to define the n
+
polysilicon layer
50
, the third silicon nitride layer
52
, and the third silicon dioxide layer
46
, thus forming the patterned n
+
polysilicon layer
50
and the patterned third silicon nitride layer
52
as shown in FIG.
1
G. Besides, a portion of the third silicon dioxide layer
46
is covered by the patterned n
+
polysilicon layer
50
still remains after the foregoing etching step. The patterned n
+
polysilicon layer
50
comprises the emitter of

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