Semiconductor device manufacturing: process – Chemical etching – Liquid phase etching
Reexamination Certificate
2001-01-05
2002-06-11
Utech, Benjamin L. (Department: 1765)
Semiconductor device manufacturing: process
Chemical etching
Liquid phase etching
C438S747000, C438S750000, C438S756000, C438S757000
Reexamination Certificate
active
06403496
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention pertains in general to shallow trench isolations in a semiconductor device and, more particularly, to a method of forming substantially planar shallow trench isolations.
2. Description of the Related Art
Shallow trench isolations (“STIs”) are used for device isolation in an integrated circuit. A conventional process of forming STIs begins by defining a wafer substrate. An insulating layer of silicon dioxide is then grown over the substrate, followed by depositing a layer of silicon nitride over the insulating layer. After shallow trenches are patterned and formed in the device substrate and through the insulating layer and the silicon nitride layer, silicon dioxide is deposited, filling the trenches and in the process forming a layer over the silicon nitride layer. Silicon dioxide deposited over the silicon nitride layer is removed, usually with chemical-mechanical polishing (“CMP”), to obtain a substantially planar surface.
However, the silicon dioxide layer, deposited by a conventional low pressure chemical vapor deposition (“LPCVD”) technique, is often thicker at the wafer edge, or “bowl-shaped.” As a result, the CMP process that leaves a substantially planar surface would also leave silicon dioxide residues over the silicon nitride layer at the wafer edge. If the residues are not removed, they act as a mask and prevent subsequent removal of the silicon nitride layer. If, however, the wafer is intentionally over-polished during the CMP process to remove the silicon dioxide at the wafer edge, the STIs closer to the center of the wafer will become bowl-shaped, i.e., non-planar, which may impede subsequent STI formation process steps.
The process continues by etching back the silicon dioxide in the trenches using a buffered oxide etch (“BOE”), a type of isotropic etching, to yield a planar surface. The silicon nitride layer serves as an etch stop for the BOE. This is followed by the removal of the silicon nitride layer with hot phosphoric acid H
3
PO
4
.
This conventional STI formation process, however, often leaves micro-trenches that result in nonplanarity of the oxide surface, at the interface between the silicon dioxide in the trenches and the device substrate. The micro-trenches present an impediment to subsequent device formation processes. The formation of micro-trenches is largely due to the BOE that leaves undesired micro-trenches between the etched material and etch-stop. When the etch-stop, i.e., silicon nitride, is stripped, the micro-trenches remain.
FIG. 1
illustrates the resulting structure. Referring to
FIG. 1
, micro-trenches
2
are formed at the interface between silicon substrate
4
and silicon dioxide
6
in shallow trenches
8
.
SUMMARY OF THE INVENTION
Accordingly, the present invention is directed to a method of forming a planar shallow trench isolation structure that substantially obviates one or more of the problems due to limitations and disadvantages of the related art.
Additional features and advantages of the invention will be set forth in the description which follows, and in part will be apparent from the description, or may be learned by practice of the invention. The objectives and other advantages of the invention will be realized and attained by the structures and methods particularly pointed out in the written description and claims hereof, as well as the appended drawings.
To achieve these and other advantages, and in accordance with the purpose of the invention as embodied and broadly described, there is provided a method for forming planar shallow trench isolations in a wafer substrate having a silicon dioxide insulating layer disposed over the substrate and a silicon nitride layer disposed over the silicon dioxide insulating layer to form a substrate-insulator-silicon nitride stack. A surface of the substrate-insulator-silicon nitride stack is planar and has a plurality of trenches filled with silicon dioxide. The method includes the steps of anisotropically etching the silicon dioxide layer to produce in the trenches silicon dioxide having sidewalls contiguous with the silicon nitride layer, and isotropically etching to remove the silicon dioxide sidewalls such that the silicon dioxide in the trenches is planar with the silicon dioxide insulating layer.
In another aspect, the step of isotropically etching includes a step of performing a buffered oxide etch.
In yet another aspect, the step of anisotropically etching includes a step of etching with faster etch rate at the edge of the wafer.
Also in accordance with the invention, there is provided a method for forming shallow trench isolations. The method includes the steps of defining a wafer substrate, forming a first insulating layer on the substrate, and depositing a second insulating layer on the first insulating layer wherein the first insulating layer is a different material than the second insulating layer. The method also includes the steps of forming at least one trench in the substrate through the first and second insulating layers, depositing a third insulating layer over the second insulating layer and in the trench wherein the third insulating layer is the same material as the first insulating layer and removing portions of the third insulating layer deposited over the second insulating layer to obtain a planar surface on the second insulating layer. The method additionally includes the steps of anisotropically etching the third insulating layer such that the third insulating layer inside the trench has sidewalls contiguous with the second insulating layer, isotropically etching to remove the sidewalls such that the third insulating layer in the trench is planar with the first insulating layer, and removing the second insulating layer.
In one aspect of the invention, the step of removing the silicon nitride layer includes a step of removal with hot phosphoric acid.
In another aspect, the step of forming a second insulating layer includes a step of depositing silicon nitride.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the invention as claimed.
REFERENCES:
patent: 5872045 (1999-02-01), Lou et al.
patent: 5893744 (1999-04-01), Wang
Finnegan Henderson Farabow Garrett & Dunner L.L.P.
Tran Binh X
Utech Benjamin L.
Windbond Electronics Corporation
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