Semiconductor device manufacturing: process – Formation of electrically isolated lateral semiconductive... – Grooved and refilled with deposited dielectric material
Patent
1999-09-09
2000-08-01
Dang, Trung
Semiconductor device manufacturing: process
Formation of electrically isolated lateral semiconductive...
Grooved and refilled with deposited dielectric material
438424, 438426, 438437, H01L 2176
Patent
active
060966238
ABSTRACT:
A method for forming a shallow trench isolation structure. A pad oxide layer is formed over a substrate. A hard mask layer is formed over the pad oxide layer. A portion of the hard mask layer, the pad oxide layer and the substrate is removed to form a trench in the substrate. Insulation material is deposited into the trench to form an insulation plug. The hard mask layer is removed to expose the sidewalls of the insulation plug. Spacers are formed on the exposed sidewalls of the insulation plug. Ions are implanted into the substrate. The pad oxide layer, the spacers and a portion of the insulation plug are removed. Finally, a gate oxide layer thicker in region around the edge of the insulation plug is formed over the substrate by oxidation.
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patent: 5733383 (1998-03-01), Fazan et al.
patent: 5930620 (1999-07-01), Wristers et al.
patent: 5960298 (1999-09-01), Kim
patent: 5989978 (1999-11-01), Peidous
Dang Trung
United Microelectronic Corp.
United Semiconductor Corp.
Wu Charles C.H.
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