Method for forming shallow trench isolation region

Details Method for forming shallow trench isolation region Method for forming shallow trench isolation region

1999-02-01

2001-01-30

Fourson, George (Department: 2823)

Semiconductor device manufacturing: process

Formation of electrically isolated lateral semiconductive...

Grooved and refilled with deposited dielectric material

Reexamination Certificate

active

06180493

ABSTRACT:

CROSS-REFERENCE TO RELATED APPLICATION
This application claims the priority benefit of Taiwan application serial no. 87117419, filed Oct. 21, 1998.
BACKGROUND OF THE INVENTION
1. Field of Invention
The present invention relates to a method for forming an integrated circuit device. More particularly, the present invention relates to a method for forming a shallow trench isolation (STI) region in a semiconductor substrate.
2. Description of Related Art
Device isolation regions are specially formed structures in a substrate for preventing carriers from moving between neighboring devices. Normally, device isolation regions are formed within a dense semiconductor circuit, for example, between the field effect transistors (FETs) inside a dynamic random access memory (DRAM) for reducing leakage current between the FETs. Conventional isolation regions are a pattern of field oxide layers formed using a local oxidation of silicon (LOCOS) method. Since the LOCOS method has been in use for fabricating devices some time, it has become one of the most cost effective and reliable methods for forming device isolation regions.
However, the field oxide layer produced by the LOCOS method often builds up internal stress. Moreover, a bird's beak profile is formed close to the edge of the field oxide layer. The presence of a bird's beak near the edge of the field oxide layer makes device isolation almost impossible especially when the dimensions of device are small. Hence, in the fabrication of high-density circuits, shallow trench isolation (STI) type of isolation structure has to be used almost exclusively.
Shallow trench isolation is a method for forming a device isolation region. The method includes the steps of anisotropically etching a semiconductor substrate to form a trench, and then depositing oxide material to fill the trench. Since the shallow trench isolation structure can be scaled and the bird's beak encroachment problem can be avoided, STI is an ideal method for isolating sub-micron complementary MOS (CMOS) devices.
FIGS. 1A through 1E
are schematic, cross-sectional views showing the progression of manufacturing steps according to a conventional method of forming a shallow trench isolation region in a substrate. First, as shown in
FIG. 1A
, a pad oxide layer
102
is formed over a silicon substrate
100
using a thermal oxidation method. The pad oxide layer
102
protects the silicon substrate
100
against damages in subsequent processing operations. Thereafter, a silicon nitride mask layer
104
is formed over the pad oxide layer
102
using a low-pressure chemical vapor deposition (LPCVD) method.
Next, as shown in
FIG. 1B
, a conventional method is used to deposit a photoresist layer (not shown) over the mask layer
104
. Then, the mask layer
104
, the pad oxide layer
102
and the silicon substrate
100
are sequentially etched. Hence, a patterned mask layer
104
a
and pad oxide layer
102
a
as well as a trench
108
are formed above the substrate
100
. Finally, the photoresist layer is removed.
Next, as shown in
FIG. 1C
, high-temperature thermal oxidation is conducted to form a liner oxide layer
110
on the exposed substrate surface of the trench
108
. The liner oxide layer
110
extends from the bottom of the trench
108
to the top corners
120
where it contacts the pad oxide layer
102
a.
Thereafter, insulating material is deposited into the trench
106
and over the silicon nitride layer
104
a
to form an insulation layer
116
. The insulation layer
116
can be a silicon oxide layer formed using, for example, an atmospheric pressure chemical vapor deposition (APCVD) method. Subsequently, the substrate
100
is heated to a high temperature so that the silicon oxide material is allowed to densify into a compact insulation layer
116
.
Thereafter, as shown in
FIG. 1D
, using the silicon nitride layer
104
a
as a polishing stop layer, chemical-mechanical polishing is carried out to remove a portion of the insulation layer
116
while retaining a portion within the trench
108
. The remaining insulating material inside the trench
108
becomes an insulation layer
116
a.
Next, as shown in
FIG. 1E
, hot phosphoric acid solution is applied to remove the silicon nitride mask layer
104
a,
thereby exposing the pad oxide layer
102
a.
Thereafter, hydrofluoric (HF) acid solution is applied to remove the pad oxide layer
102
a.
The remaining insulation layer
116
a
and liner oxide layer
110
within the trench
108
of the substrate
100
forms a complete device isolation region
118
.
In the aforementioned method of fabricating a device isolation region, the densification of insulation layer
116
is carried out in a nitrogen-filled atmosphere rather than an oxygen-filled atmosphere. This is because the trench sidewalls may oxidize in an oxygen-filled atmosphere, which may lead to an accumulation of stress in that area. Obviously, high stress in the device is highly undesirable because it can produce unwanted leakage current and reliability problems. Nevertheless, by carrying out the densification in a nitrogen-filled atmosphere, the densified insulation layer
116
is less compact. Therefore, when hydrofluoric acid solution is applied to remove the pad oxide layer
102
a
in a wet etching operation, etching rate of the insulation layer
116
may be higher than the pad oxide layer
102
a.
Hence, the combination of the wet etching of pad oxide layer
102
a
with the isotropic etching of the insulation layer
116
easily produces recess cavities
126
at the top corners
120
of the trench
108
(that is, at the junction between the insulation layer
116
and the substrate
100
). The recess cavities
126
in that region can lead to intensification of the kink effect. Consequently, besides lowering the threshold voltage, parasitic MOSFETs are also established around the corners of the device. Hence, a large leakage current may be produced.
In light of the foregoing, there is a need to improve the method of forming shallow trench isolation region.
SUMMARY OF THE INVENTION
Accordingly, the present invention provides a method for forming a shallow trench isolation region capable of densifying the insulation layer within the shallow trench such that recess cavities cannot form near the top corners of a trench. Hence, the conventional kink effect can be avoided and efficiency of the device can be improved.
To achieve these and other advantages and in accordance with the purpose of the invention, as embodied and broadly described herein, the invention provides a method for forming a shallow trench isolation (STI) region. The method includes the steps of sequentially forming a pad oxide layer and a mask layer over a substrate, and then patterning the pad oxide layer and the mask layer to form an opening. The substrate is etched to form a trench using the mask layer as an etching mask. A thermal oxidation process is carried out to form a first liner layer over the exposed substrate surface inside the trench. A second liner layer and a buffer layer, both conformal to the device profile, are sequentially formed over the substrate. A first insulation layer is formed inside the trench with the opening such that its upper surface is at a height level between the upper and the lower surface of the mask layer. A portion of the buffer layer lying above the second liner layer is removed so that the upper ends of the buffer layer are also at a level between the upper surface and the lower surface of the mask layer. A second insulation layer is formed over the first insulation layer, thereby filling the opening. The second liner layer, the mask layer and the pad oxide layer above the substrate are removed.
According to a second embodiment of this invention, a method for forming shallow trench isolation (STI) region is provided. The method includes the steps of sequentially forming a pad oxide layer and a mask layer over a substrate, and then patterning the pad oxide layer and the mask layer to form an opening. Spacers are formed on the exposed sidewalls of the mask l

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