Method for forming shallow trench isolation

Details Method for forming shallow trench isolation Method for forming shallow trench isolation

2001-05-07

2002-03-12

Bowers, Charles (Department: 2813)

Semiconductor device manufacturing: process

Formation of electrically isolated lateral semiconductive...

Grooved and refilled with deposited dielectric material

C438S426000, C438S435000, C257S510000

Reexamination Certificate

active

06355539

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method for forming a shallow trench isolation, and more particularly to a method for forming a shallow trench isolation having protective spacers on both sides without using any silicon nitride layer.
2. Description of the Related Art
As the density of integrated circuits increases, the dimension of an isolation region between active regions in semiconductor devices decreases. With this trend, the conventional local oxidation of silicon (LOCOS) method for isolating active regions, which forms a field oxide layer by using a thermal oxidation technique, confronts the limit in the effective isolation length, thereby degrading characteristics of the isolation region. Furthermore, the conventional LOCOS method possesses some inherent drawbacks resulting from the processes, i.e., lateral oxidation of the silicon underneath the silicon nitride mask, making the edge of the field oxide resemble the shape of a bird's beak.
According to the disadvantages for LOCOS isolation structures mentioned above, an isolation technique using trenches has been developed. Generally, the trench isolation includes the steps of etching a silicon substrate to form a trench, depositing a oxide layer by using a chemical vapor deposition (CVD) process to fill up the trench, providing the oxide layer a planarized surface by using a chemical l mechanical polish (CMP) process, and removing the oxide layer upon the active regions.
According to the technique, the semiconductor substrate is etched at a predetermined depth, thereby providing excellent characteristics of the device isolation. Furthermore, the field oxide layer is formed by using a CVD technique, so that the device isolation region that is defined by a photolithography process can be maintained throughout. The device isolation technique set forth is also known as shallow trench isolation (STI) processes.
However, conventional shallow trench isolation processes still have several drawbacks.
FIG. 1A
shows a cross-sectional diagram of a shallow trench isolation amid a STI conventional process. A substrate
100
, a silicon dioxide layers
102
, a silicon nitride layer
104
and a linear oxide layer
106
are also shown in FIG.
1
A. During the wet etching process to form the masking nitride layer
104
by hot phosphoric acid, the etchant also attacks the underlying polysilicon or silicon of the substrate
100
in the vicinity of the oxide layer
102
. This pitting formation seriously damages the substrate
100
thereby degrades the quality of the diffusion regions. The pitting formation is also found in the buffer polysilicon after wet nitride removal and in silicon substrate after polysilicon etching. It is attributed to a chemical reaction of water, ammonia, and silicon during wet field oxidation, similar to the so-called white-ribbon effect. The mechanism of this reaction is investigated by T. T. Sheng, et al., in the paper “From White Ribbon to Black Belt: A Direct Observation of the Kooi Effect Masking Film by Transmission Electron Microscopy”, J. Electrochem. Soc., vol. 140, p. L.163, 1993. This mechanism induces damages to the substrate and results in yield loss in deep submicron devices. To solve the problems mentioned above, modern semiconductor sector uses a sacrificial oxide layer to remove the pitting but this costs additional process step and time. Besides, owing to the high tensile stress of a silicon nitride layer which is larger than 10
9
dyne/cm
2
, additional process such as a sacrificial oxide process used to reduce the tensile stress and remove the damaged portion of the substrate is needed.
Another problem of conventional STI process results from the oxide etching process as shown in FIG.
1
B. The STI is completed by using a series of conventional processes comprising oxide filling deposition, chemical mechanical polishing and etching. As shown in
FIG. 1B
, the corners portions of STI oxide
108
have troubling fillisters which could cause leakage current and result in STI failure. The fillisters is formed because the wet etching rate on the corner portion is always higher.
In view of the drawbacks mentioned with the prior art process, there is a continued need to develop new and improved processes that overcome the disadvantages associated with prior art processes. The requirements of this invention are that it solves the problems mentioned above.
SUMMARY OF THE INVENTION
It is therefore an object of the invention to provide a STI process without using any silicon nitride thereby prevent the kooi effect and reduce the stress caused by silicon nitride.
It is another object of this invention to provide a STI structure having protective spacers to protect the corner portions of the STI.
It is a further object of this invention to provide a reliable STI process and structure which can assure the isolation quality between the active regions.
To achieve these objects, and in accordance with the purpose of the invention, the invention uses a method comprising: providing a substrate having a first dielectric layer thereon and a first conductive layer over the first dielectric layer; forming a second dielectric layer over the first conductive layer; forming a second conductive layer over the second dielectric layer; forming a trench into the second conductive layer, the second dielectric layer, the first conductive layer, the first dielectric layer and the substrate; conformally forming a linear dielectric layer over the trench; filling the trench with a dielectric material to form a trench isolation; removing the second conductive layer; forming a third dielectric layer over the second dielectric layer and the trench isolation; anisotropically etching the third dielectric layer and the second dielectric layer to expose the first conductive layer; etching the first conductive layer to expose the first dielectric layer; etching the first dielectric layer to expose the substrate; and oxidizing the substrate.
The invention avoids using any silicon nitride material to prevent the kooi effect and reduce the stress caused by silicon nitride. The invention also uses spacers to protect the corner portions of the STI. The first conductive layer comprising a polysilicon or an amorphous layer is used to replace the conventional used silicon nitride layer in the formation of conventional STI regions. The invention also uses the first dielectric layer comprising a pad oxide layer as a sacrificial oxide layer so that an additional sacrificial oxide layer is no longer needed. The high selectivity ratio between the first dielectric layer comprising a silicon dioxide layer and the first conductive layer comprising a polysilicon or an amorphous silicon layer renders the first dielectric layer undamaged in the formation of the STI of this invention. The first conductive layer comprising a polysilicon or an amorphous silicon layer will be oxidized together with the substrate in the formation of the gate oxide layer so that the isolation quality can be maintained. The spacers can protect the STI during the various process steps such as wet etching so that the isolation between adjacent active regions can be assured.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the invention, as claimed.


REFERENCES:
patent: 5506168 (1996-04-01), Morita et al.
patent: 5554256 (1996-09-01), Pruijmboom et al.
patent: 5897361 (1999-04-01), Egawa
patent: 5990002 (1999-11-01), Niroomand et al.
patent: 6096622 (2000-08-01), Kim et al.
patent: 6214696 (2001-04-01), Wu
patent: 6238997 (2001-05-01), Chen et al.
patent: 6284623 (2001-09-01), Zhang et al.

Affiliated with

Also associated with

Rating

Method for forming shallow trench isolation does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method for forming shallow trench isolation, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method for forming shallow trench isolation will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2830138