Method for forming shallow trench isolation

Details Method for forming shallow trench isolation Method for forming shallow trench isolation

2000-11-29

2001-12-18

Bowers, Charles (Department: 2813)

Semiconductor device manufacturing: process

Formation of electrically isolated lateral semiconductive...

Grooved and refilled with deposited dielectric material

C438S426000, C438S435000, C257S510000

Reexamination Certificate

active

06331472

ABSTRACT:

FIELD OF THE INVENTION
The present invention generally relates to a method for manufacturing semiconductor devices, and more particularly, to a method for forming shallow trench isolation in semiconductor devices.
BACKGROUND OF THE INVENTION
With the fast developments of semiconductor process technology, the dimensions of integrated circuits (ICs) are rapidly scaled down into sub-micron level. Oxide isolation regions are usually incorporated with active areas of IC devices during the period of semiconductor processes. In general, a local oxidation (LOCOS) process is employed to form these oxide isolation regions, but the LOCOS process may induce a bird's beak structure such that the active areas of devices are unacceptably encroached. Therefore, a shallow trench isolation (STI) process is widely used to form isolation regions between active areas. The conventional process of manufacture for shallow trench isolation is shown in FIG.
1
and FIG.
2
.
Referring to
FIG. 1
, a pad oxide layer
12
and a silicon nitride layer
14
are sequentially deposited on substrate
10
, and then a shallow trench
16
is formed thereon by an etch process. A thermal oxidation process is followed to form a lining oxide layer
18
on sidewalls of the shallow trench
16
. Next, a high-density plasma chemical vapor deposition (HDPCVD) is used to fill silicon oxide
19
into the shallow trench
16
. The excess silicon oxide
19
over the silicon nitride layer
14
is totally removed by chemical-mechanical polishing (CMP).
Referring to
FIG. 2
, the silicon nitride layer
14
is stripped by hot phosphoric acid (H
3
PO
4
) and the pad oxide layer
12
is etched away by hydrofluoric acid (HF). At the time, a silicon oxide plug
22
is remained in the shallow trench
16
. When the pad oxide layer
12
is being removed, the silicon oxide plug
22
and the lining oxide layer
18
are also simultaneously etched. Generally speaking, the etch rate of the pad oxide layer
12
formed by thermal oxidation is smaller than that of the silicon oxide plug
22
formed by HDPCVD when HF is used as an etchant. Consequently, recesses
20
located on the edge of silicon oxide plug
22
will result in current leakage and a sub-threshold voltage, which evokes many problems in device operations.
Further, while the silicon oxide
19
is deposited using HDPCVD process, the crystalline structure of shallow trench
16
surface may be damaged by a lot of ions induced by high-density plasma at the start-up time of the process. Furthermore, the isolation effect of the shallow trench
16
will severely downgrade after the silicon oxide plug
22
is entirely formed.
SUMMARY OF THE INVENTION
In view of the problems encountered with the foregoing conventional shallow trench isolation.
As a result, the primary object of the present invention is to provide a method for forming shallow trench isolation incorporated with a silicon-rich oxide layer, featured with low wet etching rate ratio and low plasma damage, using in-situ two-step deposition of HDPCVD process.
In the preferred embodiment of the present invention, a silicon-rich oxide layer used as protection layer for the shallow trench isolation is deposited by HDPCVD process. A pad oxide layer is formed on a substrate, and a mask layer is deposited on the pad oxide layer wherein the mask layer is formed by low-pressure chemical vapor deposition (LPCVD) and used as an etching mask. Afterwards, the pad oxide layer is used to prevent stress damage when the mask layer is deposited thereon. The mask layer and the pad oxide layer are patterned and the substrate is exposed. The exposed substrate is subsequently etched to form a shallow trench wherein the patterned silicon nitride layer is used as an etching mask. Subsequently, a lining oxide layer is formed by thermal oxidation on the shallow trench sidewalls. A silicon-rich oxide layer is deposited by HDPCVD process on the substrate and the shallow trench. Next, a silicon oxide layer is formed using the same HDPCVD process on the silicon-rich layer. The excess portion of silicon oxide and the silicon-rich oxide over the silicon nitride layer are effectively removed using some standard semiconductor processes, such as CMP or etching back. Thereafter, a silicon oxide plug, which serves as shallow trench isolation, is formed when the mask layer and the pad oxide layer are removed.
In summary, the process of manufacturing for shallow trench isolation is described in the present invention, wherein the silicon-rich oxide layer is used as protection for the silicon oxide plug from the recesses. Additionally, the damage of the inner surface of the shallow trench is effectively inhibited in the presence of a large amount of plasma ions, and the probability of current leakage is thereby decreased owing to the controlled defects between shallow trench and substrate. Most importantly, the throughput of manufacturing process according to the present invention will not be influenced, which in-situ two-step deposition is implemented, each step with the same HDPCVD process.


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