Semiconductor device manufacturing: process – Formation of electrically isolated lateral semiconductive...
Reexamination Certificate
1999-01-12
2001-04-10
Nelms, David (Department: 2818)
Semiconductor device manufacturing: process
Formation of electrically isolated lateral semiconductive...
C438S221000, C438S424000
Reexamination Certificate
active
06214691
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method for forming trench isolation, and particularly, to a method for forming shallow trench isolation without microscratches by using High-Density-Plasma (HDP) process.
2. Description of the Prior Art
Chemical-Mechanical polishing (CMP) is conventionally used in semiconductor manufacturing to achieve global planarity. The chemical-mechanical polishing generally includes a rotating table for holding a wafer, where slurry and a polishing pad are applied. Chemical-Mechanical polishing is usually used to planarize trenches, such as shallow trench isolation. During trench refilling step in forming a shallow trench isolation, as shown in
Figure 1A
, silicon dioxide
110
is deposited over a semiconductor substrate
112
, thereby refilling the trench
114
.
Figure 1B
shows the cross section of the formed shallow trench isolation
110
A, which is formed by planarizing the vapour deposited silicon dioxide
110
by a conventional Chemical-Mechanical polishing until the top surface of the silicon nitride layer
116
atop of the substrate
112
is exposed.
Unfortunately, due to the inherent drawbacks of the chemical-mechanical polishing mechanism, the surface of the shallow trench isolation
110
A can not be made substantially planar, and thus possesses microscratch problem which seriously yields degradation in the manufactured device.
For the foregoing reasons, there is a need for a method of forming shallow trench isolation without aforementioned microscratches problem.
SUMMARY OF THE INVENTION
In accordance with the present invention, a method is provided for forming shallow trench isolation that substantially eliminating microscratch problem.
In one embodiment, a pad oxide and SiN layers are firstly formed on a silicon substrate. The trenches are then defined by Lithography/Etch processes. After that, a thin liner is thermally grown followed by high-density-plasma (HDP) refilled oxide. Thereafter, a High-Density-Plasma (HDP) silicon oxide layer is blanket deposited over the silicon nitride layer and the trench, thereby refilling the trench, wherein top surface of the High-Density-Plasma silicon oxide layer in the trench is approximately lower than top surface of the silicon nitride layer. A photoresist layer is formed on the High-Density-Plasma silicon oxide layer, followed by etching back a portion of the photoresist layer. The High-Density-Plasma silicon oxide layer on the top of active area is isotropically etched, wherein portion of the refilled High-Density-Plasma silicon oxide layer in the trench is protected from being etched by the atop photoresist layer. Finally, the photoresist layer is removed.
REFERENCES:
patent: 5970363 (1999-10-01), Kepler et al.
patent: 6040233 (2000-03-01), Hodges
patent: 6054364 (2000-04-01), Gardner et al.
patent: 6124183 (2000-09-01), Karlsson et al.
Liu Chih-Chien
Lur Water
Yew Tri-Rung
Yong Gwo-Shii
Bacon & Thomas PLLC
Dang Phuc T.
Nelms David
United Microelectronics Corp.
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