Semiconductor device manufacturing: process – Formation of electrically isolated lateral semiconductive... – Grooved and refilled with deposited dielectric material
Patent
1997-05-27
1999-11-02
Chaudhuri, Olik
Semiconductor device manufacturing: process
Formation of electrically isolated lateral semiconductive...
Grooved and refilled with deposited dielectric material
438435, H01L 2176
Patent
active
059769491
ABSTRACT:
A method for forming shallow trench isolation that can avoid dishing effect produced by a conventional manufacturing process. The method utilizes photolithographic and etching techniques to define a dummy pattern inside a shallow trenches having a deposited dielectric layer, and then through the deposition of a second dielectric layer, followed by a planarization using a chemical-mechanical polishing method, a shallow trench isolation having a good planar surface is obtained.
REFERENCES:
patent: 4385975 (1983-05-01), Chu et al.
patent: 4615103 (1986-10-01), Kameyama et al.
patent: 4671970 (1987-06-01), Keiser et al.
patent: 5362669 (1994-11-01), Boyd et al.
patent: 5665635 (1997-09-01), Kwon et al.
patent: 5702977 (1997-12-01), Jang et al.
patent: 5804490 (1998-09-01), Fiegl et al.
patent: 5872043 (1999-02-01), Chen
Chaudhuri Olik
Duy Mai Anh
Winbond Electronics Corp.
LandOfFree
Method for forming shallow trench isolation does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method for forming shallow trench isolation, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method for forming shallow trench isolation will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2134549