Method for forming semiconductor integrated circuit using monola

Details Method for forming semiconductor integrated circuit using monola Method for forming semiconductor integrated circuit using monola

1996-09-25

1998-01-06

Niebling, John

Fishing, trapping, and vermin destroying

437108, 437112, 437128, 148DIG41, 148DIG169, H01L 21265

Patent

active

057054088

ABSTRACT:
A semiconductor integrated circuit device including: an off-substrate having a semiconductor surface with a plurality of steps each having a height of one monolayer and extending in one direction; a wiring layer formed on the semiconductor surface of the off-substrate and made of semiconductor material, the wiring layer including a plurality of conductive stripe regions and high resistance strip regions disposed in a stripe pattern, each stripe region extending in a direction parallel with the steps, and the conductive stripe regions and the high resistance stripe regions both having lattice structures identical to those of underlying surfaces; and semiconductor elements formed on the wiring layer and electrically connected to the conductive stripe regions, the semiconductor elements including semiconductor regions with lattice structures identical to those of the conductive stripe regions. Technologies of manufacturing a semiconductor element on a semiconductor substrate capable of reducing the number of fine pattern fabrication processes by photolithography or capable of dispensing with these processes.

REFERENCES:
patent: 5049951 (1991-09-01), Goronkin et al.
patent: 5311465 (1994-05-01), Mori et al.
patent: 5361720 (1994-11-01), Evetts et al.

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