Method for forming semiconductor device including a dual inlaid

Details Method for forming semiconductor device including a dual inlaid Method for forming semiconductor device including a dual inlaid

1997-11-03

2000-10-10

Tsai, Jey

Semiconductor device manufacturing: process

Having magnetic or ferroelectric component

438240, 438253, H01G 706, H01L 218242

Patent

active

061301027

ABSTRACT:
A method for forming an improved embedded DRAM structure, that is formed on-chip with CMOS logic portions, begins by forming dual inlaid regions (34a through 34c). The region (34a) is a portion of a dual inlaid region which is filled with an oxidation tolerant material (e.g., iridium or ruthenium) to form a metallic plug (36a). This plug (36a) forms a storage node region for a DRAM and electrically contacts to a current electrode (26) of a DRAM pass transistor. Opening (34b) is filled concurrently with the filling of opening (34a), to form a metallic plug (36b) which forms a bit line contact for the DRAM cell. A top portion of the dual inlaid structure (34c) is filled concurrent with regions (34a and 34b) to enable formation of a bottom electrode of the ferroelectric DRAM capacitor. Since the geometry of the region (36c) is defined by dual inlaid/CMP processing, no RIE-defined sidewall of the bottom capacitor electrode is present whereby capacitor leakage current is reduced. Furthermore, the oxygen-tolerant material used to form the plugs (36a through 36c) herein prevents adverse plug oxidation which is present in the prior art during ferroelectric oxygen annealing.

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Kohyama, et al. "A Fully Printable, Self-aligned and Planarized Stacked Capacitor DRAM Cell Technology for 1 Gbit DRAM and Beyond", 1997 Symposium on VLSI Technology Digest of Technical Papers, pp. 17-18.
Kim, et al. "Highly Manufacturable 1 Gb SDRAM", 1997 Symposium on VLSI Technology Digest of Technical Papers, pp. 9-10.

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