Semiconductor device manufacturing: process – Formation of electrically isolated lateral semiconductive... – Having air-gap dielectric
Reexamination Certificate
2000-12-21
2002-03-26
Elms, Richard (Department: 2824)
Semiconductor device manufacturing: process
Formation of electrically isolated lateral semiconductive...
Having air-gap dielectric
C438S411000, C438S421000
Reexamination Certificate
active
06362073
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a method for forming a semiconductor device; and, more particularly, to a method for forming a semiconductor device with low parasite capacitance by using an air gap and a self-aligned contact plug formed by a selective epitaxial growing method.
DESCRIPTION OF THE PRIOR ART
Generally, the refresh time, which is one of the most important features in semiconductor memory device, may be determined by a leakage current which is caused by a drain damage and this drain damage is often generated at the time of forming a charge storage node contact for electrically connecting the charge storage electrode to the drain of a transistor. The resolution of current lithography techniques may prevent a misconnection in 16M DRAM manufacturing processes or less, which may be caused by an undesired connection to other layers at sidewalls of a contact hole, but the space between the contact hole and adjacent conducting layers in an interlayer insulating layer becomes narrower with the development of the integrated circuits.
The contact is minimized in order to solve the above-mentioned problem and this problem may be solved somewhat by modifying the exposure method in a step-and-repeat projection equipment (i.e., stepper), modifying mask to define the contact hole region, or using a self-aligned contact (hereinafter, referred to as SAC).
The most highlighted process is a nitride barrier SAC (hereinafter, referred to as NBSAC) process, in which a nitride layer is used as an etching barrier layer when an oxide layer is etched for forming the contact hole. The NBSAC process may be divided into two etching processes, i.e., oxide and nitride etching processes. In the oxide etching process, polymer-inducing gases, such as C
3
F
8
and C
4
F
8
, are have been used in order to improve a selective etching rate to the nitride layer. The C
3
F
8
and C
4
F
8
gases induce a lot of polymer and then a high selective etching rate to the nitride layer may be obtain, but these gases may provoke a problem in that the oxide layer within the contact hole is not removed completely because the polymer may cause an etching stop of the oxide layer. Since the selective etching rate to the nitride layer and the etching stop of the oxide layer within the contact hole are contrary to each other, reappearance of the semiconductor devices may deteriorate and a process window of the contact hole may be narrow.
To make the process window broad, the processing conditions for etching the oxide layer is controlled by a polymer decreasing method. Accordingly, in the case where the oxide layer etching process is carried out by the polymer decreasing method, it requires that the nitride layer should be thick. However, the increase of the thickness of the nitride layer causes the contact area to be diminished and an isotropic etching process is applied to the nitride layer in order to make up for the diminution of the contact area.
Further, since the oxide layer under the nitride layer is used as an electrical insulating layer, the etching process requires that the oxide layer should be controlled by a high selective etching rate in order not to be damaged and a portion of a semiconductor substrate may be exposed at the time of etching an oxide layer in a periphery circuit area, the oxide etching process to minimize the loss of the exposed semiconductor substrate is required.
However, a conventional ion induced etcher to etch the nitride layer may not obtain such a high selective etching rate in the isotropic etching process. The recently highlighted radical etcher using the etchants, such as NF
3
and CF
4
and SF
6
, provides an isotropic etching process and a high selective etching rate to the oxide layer, but it does not provide a high selective etching rate to a silicon layer (i.e., silicon wafer) because the etching process uses the fluorine-bearing etchants. Also, the etching rate of the radical etching equipment is determined by the coherence of the oxide, nitride and silicon layers because these etchants may etch all of the oxide, nitride and silicon layers. That is, in the case where the oxide layer, nitride layer and silicon layer may be placed in the order of coherence, it is impossible to obtain a high selective etching rate to a silicon layer because the silicon layer is etched most rapidly.
As a result, the conventional NBSAC process is not sufficient for a high selective etching rate and it is more difficult to obtain a processing margin in etching the oxide, nitride and silicon layers with the decrease of the yield of the semiconductor devices.
SUMMARY OF THE INVENTION
It is, therefore, an object of the present invention to provide a method for forming self-aligned contacts using a selective epitaxial growing method.
It is another object of the present invention to provide a method for improving electrical characteristics of a semiconductor device by reducing parasite capacitance.
In the present invention, a contact plug is formed on a contact area using a selective epitaxial growing method and a self-aligned contact which is formed by a selective etching rate between an epitaxial layer and an oxide layer.
In accordance with an aspect of the present invention, there is provided a method for forming a semiconductor comprising the steps of: forming word lines over a semiconductor substrate, wherein a plurality of contact areas are formed between the word lines; forming epitaxial layers for contact plugs on the contact areas, thereby forming a resulting structure; forming air gaps on non-contact areas on which the epitaxial layers is not formed, by depositing an interlayer insulation layer on the resulting structure; and patterning the interlayer insulation layer so as to expose the epitaxial layers.
REFERENCES:
patent: 5510645 (1996-04-01), Fitch et al.
patent: 6083821 (2000-07-01), Reinberg
patent: 6130151 (2000-10-01), Lin et al.
patent: 6180453 (2001-01-01), Sung et al.
patent: 6261942 (2001-07-01), Zhou et al.
Elms Richard
Finnegan Henderson Farabow Garrett & Dunner L.L.P.
Hyundai Electronics Industries Co,. Ltd.
Pyonin Adam
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