Method for forming planarized interconnect level using selective

Details Method for forming planarized interconnect level using selective Method for forming planarized interconnect level using selective

1987-02-27

1989-03-21

Chaudhuri, Olik

Fishing, trapping, and vermin destroying

437 50, 437193, 437194, 437195, H01L 21283

Patent

active

048142859

ABSTRACT:
On the surface of a semiconductor structure containing portions to be selectively connected to an interconnection pattern, a thin conductive, uniform base layer, which promotes the growth of an interconnect conductor, is desposited. To define the interconnect structure, a thick layer of insulation material is selectively formed on the surface of the base layer with openings in the insulation layer exposing portions of the base layer that are to be connected to the interconnect layer. Next, on the portions of the base layer that are exposed by the openings in the insulation layer, a layer of interconnect metal, such as tungsten or gold, that effectively blocks the implantation of the ions through it, is selectively deposited to fill the openings in the insulation layer upon and even with the top surface of the insulation layer, so that the insulation layer and deposited metal are effectively planarized. The base layer which underlies the planarized insulator/interconnect metal layer is selectively converted to an insulator in those regions beneath the insulator but not beneath the interconnect metal by bombarding the entire structure with suitable conversion causing (e.g. oxygen or nitrogen) ions.

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