Semiconductor device manufacturing: process – With measuring or testing
Patent
1997-03-20
1999-06-15
Niebling, John F.
Semiconductor device manufacturing: process
With measuring or testing
438 17, H01L 2166
Patent
active
059131020
ABSTRACT:
A method for forming a patterned photoresist layer within an integrated circuit. The method employs a measurement parameter and a control parameter, which when at a measurement parameter target value and a control parameter target value provide a patterned photoresist layer with a target critical dimension. There is also determined a measurement parameter correlation coefficient and a control parameter correlation coefficient, each of which correlates with the patterned photoresist layer target critical dimension. When forming the patterned photoresist layer, the measurement parameter value is measured and variations of the measurement parameter from the measurement target value are compensated through varying the control parameter from the control target value while employing the measurement parameter correlation coefficient and the control parameter correlation coefficient. Through the method a patterned photoresist layer with controlled and enhanced critical dimension uniformity is formed.
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Ackerman Stephen B.
Lebentritt Michael S.
Niebling John F.
Saile George O.
Szecsy Alek P.
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