Method for forming patterned features at a semiconductor...

Details Method for forming patterned features at a semiconductor... Method for forming patterned features at a semiconductor...

2003-01-29

2004-12-21

Everhart, Caridad (Department: 2825)

Semiconductor device manufacturing: process

Chemical etching

Combined with the removal of material by nonchemical means

C438S633000, C438S628000, C257S762000, C257S758000, C257S773000, C257S775000

Reexamination Certificate

active

06833323

ABSTRACT:

FIELD OF THE INVENTION
This invention generally relates to methods for forming metal filled semiconductor features and more particularly to a method for forming patterned features at a semiconductor wafer periphery to prevent metal peeling in a subsequent CMP process.
BACKGROUND OF THE INVENTION
Sub-micron multi-level metallization is one of the key technologies for the next generation of ultra large scale integration (ULSI). The multilevel interconnects that lie at the heart of this technology require planarization of interconnect features formed in high aspect ratio apertures, including contacts, vias, metal interconnect lines and other features. Reliable formation of these interconnect features is very important to the success of ULSI and to the continued effort to increase circuit density and quality on individual substrates and die.
Copper and copper alloys have become the metal of choice for filling sub-micron, high aspect ratio interconnect features on semiconductor substrates. Copper and its alloys have lower resistivity and higher electromigration resistance compared to other metals such as, for example, aluminum. These characteristics are critical for achieving higher current densities increased device speed.
As circuit densities increase, the widths of vias, contacts, metal interconnect lines, and other features, decrease to sub-micron dimensions, whereas the thickness of the dielectric layers, through the use low-k (low dielectric constant) materials, has remained substantially constant. Consequently, the aspect ratios for the features, i.e., their height divided by width, has increased thereby creating additional challenges in adequately filling the sub-micron features with, for example, copper metal. Many traditional deposition processes such as chemical vapor deposition (CVD) have difficulty filling increasingly high aspect ratio features, for example, where the aspect ratio exceeds 2:1, and particularly where it exceeds 4:1.
As a result of these process limitations, electroplating or electrodeposition, which has previously been limited to the fabrication of patterns on circuit boards, is now emerging as a preferable method for filling metal interconnects structures such as via openings (holes) and trench line openings on semiconductor devices. Typically, electroplating uses negatively charged substrate contacted with an electrolyte including positively charged metal ions of deposition material, for example copper ions, to induce electrolytic deposition of the metal ions onto the charged substrate, for example, a semiconductor wafer. A thin metal layer (seed layer) is first deposited on the semiconductor wafer to include lining etched features to provide an electrical pathway across the surfaces. An electrical current is supplied to the seed layer whereby the semiconductor wafer surface is electroplated with an appropriate metal, for example, aluminum or copper.
One exemplary process for forming a series of interconnected multiple layers, for example, is a dual damascene process. Although there are several different manufacturing methods for manufacturing damascene structures, all such methods employ a series of photolithographic masking and etching steps, typically by a reactive ion etch (RIE). In the typical multilayer semiconductor manufacturing process, for example, a dual damascene process, a series of insulating layers are deposited to include a series of interconnecting metallization structures such as vias and metal line interconnects to electrically interconnect areas within the multilayer device and contact layers to interconnect the various devices on the chip surface. In most devices, pluralities of vias are separated from one another along the semiconductor wafer and selectively interconnect conductive regions between layers of a multi-layer device. Metal interconnect lines typically serve to selectively interconnect conductive regions within a layer of a multi-layer device. Vias and metal interconnect lines are selectively interconnected in order to form the necessary electrical connections. In forming a dual damascene structure, via openings (holes) and trench line openings are etched into the insulating layers and are back-filled with metal. The insulating layers where metal interconnect lines (trench lines) are formed are typically referred to as metallization layers and the insulating layer including interconnecting vias are referred to as inter-metal dielectric (IMD) layers. The IMD layers are preferably a low-k (low dielectric constant) insulating material which reduces signal delay times caused by parasitic capacitance. The process by which via openings (holes) and trench lines are selectively etched into the insulating layers is typically a photolithographic masking process, followed by a reactive ion etch (RIE) process, both of which are commonly known in the art.
In filling the via openings and trench line openings with metal, for example, copper, electroplating is a preferable method to achieve superior step coverage of sub-micron etched features. The method generally includes first depositing a barrier layer over the etched opening surfaces, such as via openings and trench line openings, depositing a metal seed layer, preferably copper, over the barrier layer, and then electroplating a metal, again preferably copper, over the seed layer to fill the etched feature to form, for example, vias and trench lines. Finally, the deposited layers and the dielectric layers are planarized, for example, by chemical mechanical polishing (CMP), to define a conductive interconnect feature.
Metal electroplating in general is a well-known art and can be achieved by a variety of techniques. Common designs of cells for electroplating a metal on semiconductor wafers involve positioning the plating surface of the semiconductor wafer within an electrolyte solution including an anode with the electrolyte impinging perpendicularly on the plating surface. The plating surface forms the cathode of the plating system such that ions in the plating solution deposit on the conductive portion of the plating surface.
One method for providing power to the plating surface uses, for example cathode contacts (e.g., pins, ‘fingers’, or springs) to contact the plating surface which includes a featureless area including a seed layer of metal. The cathode contacts make contact with the cathode contact area which includes a seed layer blanket deposited as close as possible to the semiconductor wafer periphery to minimize the featureless area on the wafer. In the prior art, the seed layer deposited at the wafer periphery has typically been formed over an uppermost insulating (IMD) layer devoid of etched semiconductor features such as vias and trench lines. A shortcoming in the prior art is that, frequently, a subsequent CMP process following the electroplating process to remove excess metal, for example, copper overlying the IMD layer, causes delamination or peeling of the electroplated copper layers especially at the wafer periphery. The CMP induced peeling is believed to be due to poor adhesion between the copper and the underlying layers including a barrier/adhesion layer formed over the IMD layer.
The problem is exacerbated by the use of low-k (low dielectric constant) material used for the IMD layers, for example, having a dielectric constant less than about 3.0. Many of the low-k materials are designed with a high degree of porosity to allow the achievement of lower dielectric constants. A shortcoming of using porous low-k materials is that the low-k IMD layers have poor adhesion to other materials including the copper layers and adhesion/barrier layers, for example, tantalum nitride (TaN) which is frequently deposited over the IMD layer to prevent copper diffusion into the IMD layer. As a result, metal layers, for example, copper, are prone to delamination (peeling), particularly at the process wafer periphery when they are subjected to processing stresses, for example, stresses induced by subsequent metal CMP processes.
There is therefore a need in the semiconductor proc

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