Method for forming oxide isolated integrated injection logic sem

Details Method for forming oxide isolated integrated injection logic sem Method for forming oxide isolated integrated injection logic sem

1978-12-26

1979-09-25

Rutledge, L. Dewayne

Metal treatment

Process of modifying or maintaining internal physical...

Chemical-heat removing or burning of metal

29578, 148 15, 148187, 156654, 156657, 156659, 156662, 357 36, 357 46, 357 50, 357 91, 357 92, H01L 2120, H01L 2122

Patent

active

041689992

ABSTRACT:
A process for fabricating integrated injection logic structures including both vertical and lateral bipolar transistors in oxide isolated pockets of silicon includes the steps of forming a patterned composite silicon nitride-silicon dioxide layer to serve as a transistor emitter and self-aligned base mask, and introducing desired impurities to form the lateral transistor emitter and collector. The mask is partially removed and additional impurities introduced to form the vertical transistor base and vertical transistor collector.
The process does not require the use of vapor deposited silicon dioxide to pattern the wafer surface, and therefore reduces pinhole defects and the encroachment of the field oxidation on the epitaxial silicon pocket in which devices are formed. The process also results in a flatter topography to allow more uniform and reliable metal interconnections.

REFERENCES:
patent: 3564443 (1971-02-01), Nagata
patent: 3962717 (1976-06-01), O'Brien
patent: 3993513 (1976-11-01), O'Brien
patent: 4058419 (1977-11-01), Tokumaru et al.
patent: 4110125 (1978-08-01), Beyer
patent: 4110126 (1978-08-01), Bergeron et al.
patent: 4111724 (1978-09-01), Ogive et al.
patent: 4115797 (1978-09-01), Hingarh et al.

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