Method for forming multilayer wirings on a semiconductor device

Details Method for forming multilayer wirings on a semiconductor device Method for forming multilayer wirings on a semiconductor device

1991-01-02

1992-02-25

Hearn, Brian E.

Fishing, trapping, and vermin destroying

437195, 437199, H01L 2144

Patent

active

050913409

ABSTRACT:
A wiring method for semiconductor device includes the steps of forming a first seat in a portion where a lower wiring layer and an upper wiring layer are to be connected on a semiconductor substrate provided with semiconductor elements, forming a first conductor composed of an Al or Al-Cu alloy on the whole surface of the semiconductor substrate; forming the lower wiring layer by selectively removing the first conductor simultaneously with the formation of a second seat composed of the first conductor on the first seat; forming by the coating method a glass or organic silicon compound film as an interlevel insulating film, forming a through-hole by photoetching in the portion where the upper and lower wiring layers are to be connected; and forming a second conductor in order to form the upper wiring layer by photoetching.

REFERENCES:
"Semiconductor World", No. 10, 1984, pp. 129-133, ibid. No. 3, 1987, pp. 36-42.
"Nikkei Microdevices", No. 1, 1988, p. 19.

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