Semiconductor device manufacturing: process – Having magnetic or ferroelectric component
Reexamination Certificate
2002-05-17
2004-04-06
Le, Dung A. (Department: 2818)
Semiconductor device manufacturing: process
Having magnetic or ferroelectric component
C438S257000
Reexamination Certificate
active
06716644
ABSTRACT:
FIELD OF INVENTION
The present invention relates to a magnetic random access memory (MRAM) and a fabricating method thereof, and more particularly to a method of forming an MRAM cell having a bottom sense layer.
BACKGROUND OF THE INVENTION
Magnetic random access memories (MRAMs) employ memory cells having magnetic multilayer films as storage elements. When in use, an MRAM cell stores information as digital bits, in the form of relative magnetic orientations of spaced thin magnetic multilayer films forming each memory cell. Each MRAM cell has two stable magnetic film orientations, one which produces a high resistance across the cell representing e.g. a logic state 0 and another which produces a lower resistance across the cell representing e.g. a logic state 1, or vice versa.
A typical multilayer-film MRAM array includes a number of bit or digit (column) lines intersected by a number of word (row) lines. An MRAM cell is formed between a digit and row line at each intersection.
The basic memory MRAM cell has a first pinned ferromagnetic layer and a second free (sense) magnetic layer with a nonmagnetic layer between them. The pinned ferromagnetic layer has a fixed magnetic orientation while the free (sense) layer may have two different magnetic orientations, depending on the logical data stored in the cell. Each of the ferromagnetic layers is actually formed of a stack of as many as ten different overlapping material layers. Fabrication of such stacks requires deposition of the thin materials layer by layer, according to a predefined order.
FIG. 1
shows an exemplary conventional MRAM structure including MRAM cells
22
formed as layer stacks which have three respective associated bit or digit lines
18
. The digit lines
18
, typically formed of copper (Cu), are first formed in an insulating layer
16
formed over underlayers
14
of an integrated circuit (IC) substrate
10
. Underlayers
14
may include, for example, portions of integrated circuitry, such as CMOS circuitry. A pinned layer
20
, typically formed of ferromagnetic materials, is provided over each digit line
18
. A nonmagnetic layer of, for example, Al
2
O
3
is formed over the pinned layer
20
. A free (sense) layer
21
is provided over the nonmagnetic layer. The MRAM cells
22
are coupled to a word line
23
that intersects three pinned layers
20
and associated cells
22
. The word line
23
and bit line
18
may also be interchanged.
FIG. 2
illustrates a side sectional view of the MRAM stacks
22
of FIG.
1
. As shown, pinned layer
20
and sense layer
21
are comprised of several individual layers, including a bottom conductive barrier layer
24
formed of, for example, Ta, at the base of the pinned layer
20
. The barrier layer
20
also lines the trenches in which the bit lines
18
are formed. Also, pinned layer
20
and sense layer
21
are separated by a magnetically and electrically nonconductive tunnel junction layer
25
, for example, A
1
2
O
3
.
Typically, during an etching step to define the cells
22
, utilizing, for example, ion milling, the conductive layer
24
may sputter back onto the sidewall of stacks
22
forming a side conductive layer
26
creating an undesirable electrical short between the pinned
20
and sense
21
layers. Thus, during a read operation, the current may flow through the side conductive layer
26
rather than flow through the tunnel junction layer
25
, because of a short produced by layer
26
causing improper resistance sensing. Hence, what is needed is a method of fabricating an MRAM cell which will not create a short as described above.
SUMMARY OF THE INVENTION
The present invention provides a method of forming an MRAM bit having a bottom sense layer utilizing electroless plating. In an exemplary embodiment of the invention, a first conductor in a trench is provided in an insulating layer and an upper surface of the insulating layer and the first conductor is planarized. Then, a dielectric layer is deposited to a thickness slightly greater than the desired thickness of the sense layer, which is formed later. The dielectric layer is then patterned and etched to form an opening or formed cell shapes over the first conductor. Then, a permalloy is electroplated in the formed cell shapes to form the sense layer. The formed sense layer is pre-sputter cleaned and then a tunnel barrier layer is deposited. Finally, the pinned layer is formed over the tunnel barrier layer.
The above advantages and features of the invention as well as others will be more clearly understood from the following detailed description which is provided in connection with the accompanying drawings.
REFERENCES:
patent: 6172902 (2001-01-01), Wegrowe et al.
patent: 2003/0119210 (2003-06-01), Yates et al.
Deak James G.
Nejad Hasan
Dickstein , Shapiro, Morin & Oshinsky, LLP
Le Dung A.
Micro)n Technology, Inc.
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