Method for forming MOS transistor

Details Method for forming MOS transistor Method for forming MOS transistor

2005-08-16

2005-08-16

Tsai, H. Jey (Department: 2812)

Semiconductor device manufacturing: process

Formation of electrically isolated lateral semiconductive...

Grooved and refilled with deposited dielectric material

C438S629000, C438S672000

Reexamination Certificate

active

06930019

ABSTRACT:
Disclosed is a MOS transistor formation method including the steps of: forming a gate oxide film and a gate electrode on a device region of a silicon substrate; forming a nitride film spacer on one side surface of the gate electrode; forming an interlayer dielectric layer on an upper surface of overall structure inclusive of the nitride film spacer; forming a landing plug contact hole by over-etching the interlayer dielectric layer and an active region of the silicon substrate; forming an oxide film on an upper surface of overall structure inclusive of the landing plug contact hole; forming a side wall oxide film spacer by selectively eliminating the oxide film so that the oxide film remains only on a side wall of the landing plug contact hole; forming a first landing plug pattern in a lower portion of the landing plug contact hole; eliminating exposed side wall oxide film spacer and etching inside of a first landing plug pattern, thereby forming an auxiliary groove which expands area of the landing plug contact hole; and forming a second landing plug pattern in the landing plug contact hole including the first landing plug pattern and the auxiliary groove.

REFERENCES:
patent: 6858529 (2005-02-01), Chung et al.

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