Semiconductor device manufacturing: process – Formation of electrically isolated lateral semiconductive... – Having air-gap dielectric
Reexamination Certificate
1999-12-29
2002-01-29
Mills, Gregory (Department: 1763)
Semiconductor device manufacturing: process
Formation of electrically isolated lateral semiconductive...
Having air-gap dielectric
C438S212000, C438S421000, C438S400000, C216S002000, C216S041000
Reexamination Certificate
active
06342427
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a method for forming a cavity in a silicon layer and, more particularly to a method for forming a micro cavity in a silicon layer by the conventional semiconductor manufacturing process, which can be suitable for manufacturing various semiconductor sensors, minute vacuum devices or micro electro mechanical systems.
In general, two kinds of methods for forming a cavity in silicon substrate have been known. The first method is applied to form a cavity having a relatively large size. As for the first method, a sacrificial oxide layer is filled in a portion of a silicon substrate where the cavity will be formed and a thin film having an etch selectivity different from that of the oxide layer is formed on the oxide layer as a shape of a mold. Then, the sacrificial layer is removed by etching through an etching hole or an etching channel to form the cavity in the silicon substrate after the etching hole is formed through the thin film. Finally, the cavity is sealed by thin film deposition process.
When the cavity has a relatively small size, the second method disclosed at U.S. Pat. No. 5,296,408 (issued to Robert R. Wilbarg et al.) is suitable for forming the cavity. In the second method, a metal is buried in a portion of a silicon substrate where the cavity will be formed. In order to fill up the cavity the metal should be thermally diffused for a sacrificial material such as aluminum.
When the cavity has a large size, the above-mentioned methods, however, may have some disadvantages that the etching selectivities of the thin films may not be exactly controlled for forming the cavity, the processing time may increases and the flatness of the substrate is hardly maintained.
SUMMARY OF THE INVENTION
Considering the above-mentioned problems, it is an object of the present invention to provide a method for forming a micro cavity, which can enable additional patterns and devices such as temperature detecting device to be easily formed on a silicon oxide layer by forming the silicon oxide layer on a silicon layer as a sealing layer for the cavity.
It is another object of the present invention to provide a method for forming a micro cavity, which can easily form the cavity to have a large size by utilizing the conventional etching and oxidation processes.
To achieve the above-mentioned objects of the present invention, there is provided a method for forming a micro cavity.
In the method for forming the micro cavity according to the present invention, a first layer is formed on a silicon layer and a trench is formed in the silicon layer by selectively etching the silicon layer. The first layer has an etch selectivity different from the silicon layer and is composed of a silicon oxide deposited by a low pressure chemical vapor deposition method. The trench formed by using the first layer as an etching mask has a shape in which a plurality of lines and a plurality of spaces alternatively repeated. Preferably, a ratio of widths between the lines and the spaces is about 0.7~1.0:1.0~1.3.
Subsequently, a second layer having an etch selectivity different from the silicon layer is formed on the trench and on the silicon layer. The thickness of the second layer is preferably more than a half of a width of the line. The second layer can be composed of a silicon oxide formed by a thermal oxidation method at a temperature of about 950° C. to about 1100° C.
A third layer is formed on the second layer after a portion of the second layer formed on the silicon layer is removed by using a 6:1 buffered hydrogen fluoride solution as an etchant. The third layer has an etch selectivity different from the second layer and the silicon layer can be composed of a poly silicon deposited by a low pressure chemical vapor deposition method at a temperature of about between about 600° C. and about 650° C.
A plurality of etching holes having hexagonal shapes or circular shapes are formed through the third layer by partially etching the third layer, and then the second layer is removed through the etching holes by a wet etch method and by using a hydrogen fluoride solution as an etchant.
Finally, a cavity is formed between the silicon layer and the third layer.
According to one preferred embodiment of the present invention, the method for forming the micro cavity further comprises the step of closing the etching holes by thermally oxidizing the third layer.
Also, according to another preferred embodiment of the present invention, the method for forming the micro cavity further comprises the step of partially closing the etching holes by thermally oxidizing the third layer and vacuumizing the cavity by depositing an oxide layer or a nitride layer on the third layer by a chemical vapor deposition method under a low vacuum atmosphere.
The ratio of the volume expansion is generally about 2.27 when the silicon layer or the poly silicon layer is transformed into the silicon oxide layer. In other words, the silicon layer has the volume about 2.27 times larger than the volume of the silicon layer or the poly silicon layer. Therefore, the etching holes can be completely closed due to the volume expansion of the third layer.
Meanwhile, in a process for forming a vacuum cavity according to another embodiment of the present invention, the etching holes have larger sizes in order to be partially opened after the third layer is thermally oxidized considering the volume expansion of the third layer. That is, the etching holes have the size larger than the increased area of other portion of the third layer during the thermal oxidation process. Thus, the etching holes are not completely closed but partially opened, so the vacuum cavity can be formed after the CVD oxide layer or the nitride layer is formed on the third layer having the partially opened etching holes under the low vacuum atmosphere.
According to the present invention, the cavity can be easily formed and sealed in the silicon layer by utilizing the volume expansion of the silicon or the polysilicon layer and by the conventional semiconductor manufacturing technique according to the present invention.
Also, the subsequent processes such as the photolithography process and the thermal oxidation process can be facilely accomplished because the polysilicon layer is evenly formed and covered with the cavity in the silicon layer.
Furthermore, the vacuum micro cavity can be formed according as the low vacuum CVD oxide layer or a nitride layer formed on the etching holes which are partially opened after the thermal oxidation process by controlling the size of the etching holes concerning the other portion of the poly silicon layer as occasion demands.
REFERENCES:
patent: 4888300 (1989-12-01), Burton
patent: 5203731 (1993-04-01), Zimmerman
patent: 5296408 (1994-03-01), Wilbarg et al.
patent: 6211056 (2001-04-01), Begley et al.
Parameswaran, et al.; Silicon Pressure Sensors Using a Wafer-Bonded Sealed Cavity Process; Jun. 25-29, 1995; pp. 582-585.
Liu, et al.; Sealing of Micromachined Cavities Using Chemical Vapor Deposition Methods: Characterization and Optimization; Jun. 1999; pp. 135-145.
Choi Chang Auck
Jang Won Ick
Jun Chi Hoon
Kim Yun Tae
Electronics and Telecommunications Research Institute
Hassanzadeh P.
Jacobson & Holman PLLC
Mills Gregory
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