Method for forming metallization layer of wiring in semiconducto

Details Method for forming metallization layer of wiring in semiconducto Method for forming metallization layer of wiring in semiconducto

1992-04-21

1993-06-15

Quach, T. N.

Fishing, trapping, and vermin destroying

437 9, 437173, 437188, 437190, H01L 21283, H01L 21607

Patent

active

052197905

ABSTRACT:
A method for forming a metallization layer for wiring in a semiconductor integrated circuit, which includes the steps of: (1) forming an interlayer insulator on a Si substrate used to form a semiconductor device; (b) forming a contact hole extending through the interlayer insulator down to a surface of the Si substrate on which surface is deposited a TiW or TiN film; (c) depositing an Al or Al alloy film on the interlayer insulator as well as on the TiW or TiN film in the contact hole; and (d) in a high-pressure inert gas atmosphere, heating the thus processed substrate to a temperature at which the Al or Al alloy film is fused, while vibrating the entire substrate with ultrasonic waves.

REFERENCES:
patent: 4758533 (1988-07-01), Magee et al.
patent: 4920070 (1990-04-01), Mukai
patent: 4997518 (1991-03-01), Madokoro
Wolf, et al., Silicon Processing for VLSI Era, vol. 1 Process Technology, Lattice Press, 1986, pp. 331-334.
Wolf. S., Silicon Processing for VLSI Era, vol. 2 Process Integration, Office Press, 1990, pp. 124-133.

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