Method for forming metallization in an integrated circuit

Details Method for forming metallization in an integrated circuit Method for forming metallization in an integrated circuit

1993-03-01

1994-01-04

Quach, T. N.

Fishing, trapping, and vermin destroying

437183, 437228, 437944, 437230, 437190, 437192, 437229, 156653, 156656, 1566591, H01L 21283, H01L 2131

Patent

active

052759733

ABSTRACT:
Metallization having a self-aligned diffusion barrier or seed layer is formed in an integrated circuit. In one embodiment of the invention, a sacrificial material (20) is used to define a seed layer (24). A dielectric layer (26) is then formed and the sacrificial material (20) is subsequently removed to expose the underlying seed layer (24). A conductive layer of material (32), such as copper, is then selectively deposited onto the seed layer (24). Because the diffusion barrier or seed layer is self-aligned the metal to metal spacing in an integrated circuit may be reduced. Therefore, integrated circuits having high device packing densities can be fabricated.

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