Method for forming metal layer of semiconductor device

Details Method for forming metal layer of semiconductor device Method for forming metal layer of semiconductor device

2002-05-23

2004-08-24

Vinh, Lan (Department: 1765)

Semiconductor device manufacturing: process

Chemical etching

Vapor phase etching

C438S710000, C438S712000, C438S720000, C216S057000, C216S067000

Reexamination Certificate

active

06780777

ABSTRACT:

BACKGROUND OF THE DISCLOSURE
1. Field of the Disclosure
The disclosure relates to a method for flatly stacking a metal layer of a semiconductor device, and more particularly, to a method for forming a metal layer of a semiconductor device.
2. Description of Related Technology
Generally, as the integrity of a semiconductor device increases, the contact area decreases and the aspect ratio representing a degree of inclination of an etching portion increases. Usually, as the area of a contact hole decreases and the aspect ratio increases, the step coverage of a portion such as a contact hole decreases. Thus, the flow of the current becomes worse and a resistance value becomes lower, thereby degrading the reliability of the semiconductor device.
The process temperature, electric power, pressure, etc. are factors affecting the step coverage of the metal layer in methods depositing a metal layer on the contact hole. Although the step coverage of the metal layer can be enhanced by adjusting electric power and pressure, this process has some restrictions. Particularly, the step coverage can be adjusted with the temperature. However, if the temperature is too high, metal stacked on the side walls of the contact hole is diffused to another portion (e.g., interlayer insulating film) and thus a metallic line is disconnected. On the contrary, if the temperature is low, the metallic line is connected, but the step coverage is increased due to a shadowing effect making the flow of metal worse.
In this way, by a metal contact process for a highly integrated memory device of 256 megabytes or more, tungsten (W) is deposited in the contact hole by a CVD (chemical vapor deposition) process and then the resulting tungsten layer is planarized by an etch-back process.
However, in the process for stacking a tungsten layer in the contact hole and planarizing the same by the etch-back process, there are problems such as that a large number of steps are required and thus the unit cost is high, and the etch-back process is not controlled precisely and thus the tungsten layer is excessively etched.
In addition, the resistance of tungsten is relatively larger compared to that of aluminum or copper, so the contact resistance is high.
SUMMARY OF THE DISCLOSURE
Therefore, the disclosure provides a method for forming a metal layer of a semiconductor device. The disclosed method may also improve step coverage of the bottom surface and side walls of the contact hole.
The disclosed method may prevent defects caused by the disconnection of metal wire of a semiconductor device, and be economical.
The disclosed method includes the steps of continuously forming a lower conductive layer and an inter-layer insulating film on a wafer having a predetermined substructure; forming a contact hole by etching a predetermined portion of the interlayer insulating film whereby the lower conductive layer is exposed; removing moisture contained in the contact hole and the inter-layer insulating film of the wafer by degassing; forming a metal junction layer on an entire surface of the contact hole and the inter-layer insulating film thereby connected to the lower conductive film; forming a first metal layer on the metal junction layer; forming a second metal layer on the first metal layer; and forming a pattern by masking etching after coating an anti-reflection film on the second metal layer.


REFERENCES:
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patent: 5731246 (1998-03-01), Bakeman et al.
patent: 6002175 (1999-12-01), Maekawa
patent: 6217721 (2001-04-01), Xu et al.
patent: 6486555 (2002-11-01), Asahina et al.

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