Electrolysis: processes – compositions used therein – and methods – Electrolytic coating – Coating selected area
Reexamination Certificate
1999-09-09
2001-04-24
Gorgos, Kathryn (Department: 1741)
Electrolysis: processes, compositions used therein, and methods
Electrolytic coating
Coating selected area
C205S118000, C205S122000, C205S123000, C205S126000
Reexamination Certificate
active
06221229
ABSTRACT:
BACKGROUND OF THE INVENTION
U.S. Pat. No. 4,804,615 discloses a method for forming metallic conductor patterns with solderable connection regions, in which the starting point is an electrically insulating, flat substrate laminated with copper on both sides. After through-contact holes have been drilled, a copper layer, which also extends over the walls of the hole, is deposited from a chemical deposition bath. An electrolytic resist is then applied to this copper layer and covers everything except the subsequent connection regions, so that copper and a tin/lead alloy can be deposited here electrolytically one after another. The tin/lead alloy forms a final surface of the connection regions which can be soldered. After the complete removal of the electrolytic resist, an etch resist is applied and, with the exception of the connection regions, covers all the regions of the subsequent conductor pattern. After this, all those regions of the chemically deposited copper layer which do not correspond to the conductor pattern, and of the copper lamination, are etched away down to the surface of the substrate. During this etching process, it is not only the actual etch resist but also the etch-resistant final surface of the connection regions which protect the copper located beneath them from the etching attack. After the complete removal of the etch resist, a solder-stop lacquer is then applied, which covers everything except those connection regions of the conductor pattern which can be soldered.
U.S. Pat. No. 4,608,274 discloses a further method for forming metallic conductor patterns with connection regions which can be soldered, and the starting point for the method is a pre-drilled, electrically insulating, flat substrate. After the non-electrolytic deposition of copper to both sides of the substrate and in the holes, an etch resist is applied to the copper layer, and, with the exception of the subsequent connection regions, covers all the regions of the subsequent conductor pattern. An electrolytic resist is then applied, and covers everything except the subsequent connection regions, so that copper and a tin/lead alloy can be deposited electrolytically here one after another. Following the complete removal of the electrolytic resist, all the regions of the exposed copper layer are etched away, down to the surface of the substrate; and in the region of the conductor pattern, the etch resist and the etch-resistant final surface of the connection regions protect the copper layer located beneath them from the etching attack. Following the complete removal of the etch resist, a solder-stop lacquer is also applied again, and covers everything except the connection regions of the conductor pattern which can be soldered.
WO 95/29573 discloses a further method for forming metallic conductor patterns having connection regions that can be soldered and/or bonded on electrically insulating substrates. This method comprises the following method steps:
a.) Applying a metalization to the substrate;
b.) Applying an organic, electrolysis-resistant and etch-resistant protective layer to the metalization in an electrolytic dip-coating bath;
c.) Removing the protective layer in the subsequent connection regions by means of laser radiation;
d.) Electrolytically depositing an etch-resistant final surface which can be soldered and/or bonded onto those regions of the metalization exposed in method step c);
e.) Removing the protective layer, at least in the regions directly adjacent to the subsequent conductor pattern, by means of laser radiation;
f.) Etching those regions of the metalization exposed in method step e) down to the surface of the substrate.
The advantages of the method outlined above reside in particular in the fact that only a single organic protective layer has to be applied in an electrolytic dip-coating bath and, following a first structuring by means of laser radiation, serves as an electrolytic resist and, after a second structuring by means of laser radiation, serves as an etch resist, and also does not have to be removed following the formation of the conductor pattern. The protective layer previously already used as a electrolytic resist and etch resist can, if appropriate, additionally be used further as a solder-stop mask.
In WO 96/09646, a so-called Polymer Stud Grid Array (PSGA) is described which combines the advantages of a Ball Grid Array (BGA) with the advantages of MID technology. The description of the new design type as a polymer stud Grid Array (PSGA) was carried out in this case following the model of the Ball Grid Array (BGA), and the term “Polymer Stud” is intended to refer to the polymer studs formed at the same time during the injection molding of the substrate. The new design type, suitable for single-chip, few-chip or multi-chip modules, comprises
an injection-molded, three-dimensional substrate made of an electrically insulating polymer,
polymer studs arranged over the area of the underside of the substrate and formed at the same time during the injection molding,
external connections formed on the polymer studs by a final surface that can be soldered,
conductor trains, formed at least on the underside of the substrate, which connect the external connections to internal connections and
at least one chip arranged on the substrate, whose connections are electrically conductively connected to the internal connection.
U.S. Pat. No. 4,289,575 discloses a method of producing printed circuits in which, firstly, a conductor pattern is produced by means of conventional photo-etching technology, and its individual conductors remain connected to one another via connecting webs. An electrically insulating, electrolysis-resistant and etch-resistant first film is subsequently applied in such a way that only the connection regions of the conductor pattern and the connecting webs remain free. After that, an electrolysis-resistant second film is applied to the connecting webs, whereupon a final surface which can be soldered and/or bonded is applied, by means of electrolytic metal deposition, to the exposed connection regions of the conductor pattern. Following the removal of the second film, the connecting webs can then be etched away selectively.
SUMMARY OF THE INVENTION
The invention is based on the problem of providing a simple and economical method for forming metallic conductor patterns having connection regions that can be soldered and/or bonded on an electrically insulating substrate read, in particular, is also suitable for the production of flexible circuits and Polymer Stud Grid Arrays (PSGA). With regard to the requirements placed on modern chip packages, it should be possible for conductor patterns having extremely fine structures to be formed on the substrate.
The basis for the solution according to the invention is fine laser structuring, which makes it possible to implement, on a processing area of, for example 5×5 cm
2
, structures of about 40 &mgr;m conductor width and 30 &mgr;m insulation spacing, without clean-room conditions. Very dense, one-layer wiring between single-row or multiple-row chip connections, and multi-row printed circuit board connections can be implemented in this way.
Exemplary embodiments of the invention are illustrated in the drawing and will be described in:
REFERENCES:
patent: 4289575 (1981-09-01), Matsumoto et al.
patent: 4608274 (1986-08-01), Wooten
patent: 4804615 (1989-02-01), Larson et al.
patent: 5929516 (1999-07-01), Heerman et al.
patent: 0 452 506 (1991-10-01), None
patent: 0 517 399 (1992-12-01), None
patent: 0 641 152 (1995-03-01), None
patent: WO 95/29573 (1995-11-01), None
patent: WO 96/09646 (1996-03-01), None
Abstract of Japanese 08-148809,Patent Abstracts of Japan, vol. 96, No. 10, Oct. 31, 1990.
Abstract of Japanese 08-167769,Patent Abstracts of Japan, vol. 96, No. 10, Oct. 31, 1996.
De Steur Hubert
Heerman Marcel
Gorgos Kathryn
Keehan Christopher M
Schiff & Hardin & Waite
Siemens S.A.
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