Method for forming junction electrode of semiconductor device

Details Method for forming junction electrode of semiconductor device Method for forming junction electrode of semiconductor device

2001-06-22

2003-12-23

Lebentritt, Michael S. (Department: 2824)

Semiconductor device manufacturing: process

Formation of electrically isolated lateral semiconductive...

C438S183000, C438S294000, C438S300000, C438S601000

Reexamination Certificate

active

06667220

ABSTRACT:

BACKGROUND
1. Technical Field
The disclosed method relates to a method for forming a junction electrode of a semiconductor device, and in particular to an improved method for forming a junction electrode of a semiconductor device that prevents a defect due to an implantation. The method improves yield by forming a gate on a semiconductor substrate through use of a predetermined device structure, forming a contact hole by stacking an interlayer insulation film on the gate, and forming n-type and p-type junction electrodes in the contact hole according to an epitaxial growth method.
2. Description of the Background Art
In general, when fabricating a semiconductor device using an n-MOS and p-MOS, a device isolation film is formed on a semiconductor substrate and a gate oxide film and a gate electrode layer are stacked thereon, thereby forming a gate. An interlayer insulation film is stacked on the gate, thereby forming a contact hole to be connected to the gate and active regions. Thereafter, n-type and p-type junction electrodes are formed in the contact hole to connect interconnection lines of the upper and lower layers.
FIGS. 1
a
to
1
g
illustrate sequential steps of a conventional method for forming a junction electrode of a semiconductor device.
As illustrated in
FIG. 1
a,
a gate(not shown) is formed on a semiconductor substrate
1
having a predetermined device structure. An interlayer insulation film
2
is stacked over the resultant structure, and a masking etching is performed thereon to form an n-type contact hole
3
and a p-type contact hole
4
connected to the gate or active regions.
As depicted in
FIG. 1
b,
a polysilicon layer
5
is filled in the n-type and p-type contact holes
3
and
4
. A first photoresist film
6
is then stacked with an opening exposing a portion of the polysilicon layer
5
over the n-type contact hole
3
. Thereafter, n-type ions
7
are implanted into the opening of the first photoresist film
6
, thereby forming an n-type electrode
8
as shown in
FIG. 1
c.
Referring to
FIG. 1
d,
the first photoresist film
6
is removed, and a second photoresist film
9
is stacked with an opening exposing the polysilicon layer
5
over the p-type contact hole
4
. Thereafter, p-type ions
10
are implanted into the opening, thereby forming a p-type electrode
11
as shown in
FIG. 1
e.
As illustrated in
FIG. 1
f,
a pattern photoresist film
12
is formed over a prescribed portion of the polysilicon layer that correspond to desired positions of n-type and p-type junction electrodes
14
and
16
(shown in
FIG. 1
g
) and an unnecessary portion of the polysilicon layer
5
is removed to form the n-type and p-type junction electrodes
14
and
16
shown in
FIG. 1
g.
FIGS. 2
a
and
2
b
illustrate sequential steps of another conventional method for forming a junction electrode of a semiconductor device, which is almost identical to the above-described method. However, a spacer film
18
is stacked on the n-type and p-type contact holes
3
and
4
formed by etching the interlayer insulation film
2
, and the n-type and p-type electrodes
14
,
16
are formed by etching the resultant structure. As a result, spacers
19
are formed on the inside walls.
The conventional methods described previously form the p-type and n-type junction electrodes based on the ion implantation process. However, a growth-type impurity may be generated in depositing a silicon film, a silicon oxide film or a silicon nitride film in a succeeding process, thereby reducing a yield of the semiconductor device. In particular, a source gas must be alternately used, which results in poor production.
In addition, a height of the junction electrode must be restricted in the implantation process. In the case that the source gas is insufficient during production of a final electrode junction portion, a depletion may occur that deteriorates a characteristic of the semiconductor device. Moreover, the mask process must be carried out about three times, which increases the prime cost of mass production.
SUMMARY OF THE DISCLOSURE
In response to the shortcomings of the convention art, a method is disclosed for forming a junction electrode of a semiconductor device that prevents defects due to implantation, thereby improving the yield of semiconductor devices. The disclosed method for forming a junction electrode includes forming an n-type contact hole by stacking an interlayer insulation film on a semiconductor substrate having a predetermined device structure and then stacking a first photoresist film on the inter layer insulation film. Masking etching on the resultant structure is then performed to form the n-type contact hole. Next, an n-type junction electrode is grown in the n-type contact hole using a selective epitaxial growth method. The first photoresist film is then removed. A p-type contact hole is then formed by stacking a second photoresist film and masking etching the resultant structure. The second photoresist film is then removed and the p-type contact hole is filled with a spacer film. A third photoresist film is then stacked except for a portion over the p-type contact hole. Spacers are then formed out of the spacer film on inside walls of the p-type contact hole. Finally, a p-type junction electrode is grown by growing silicon in the p-type contact hole using the selective epitaxial growth method.


REFERENCES:
patent: 4400411 (1983-08-01), Yuan et al.
patent: 4464824 (1984-08-01), Dickman et al.
patent: 5413947 (1995-05-01), Kim et al.
patent: 5432104 (1995-07-01), Sato
patent: 5733827 (1998-03-01), Tehrani et al.
patent: 5753555 (1998-05-01), Hada
patent: 5840613 (1998-11-01), Sato
patent: 5972741 (1999-10-01), Kubo et al.
patent: 5976936 (1999-11-01), Miyajima et al.
patent: 6342421 (2002-01-01), Mitani et al.
patent: 6372583 (2002-04-01), Tyagi
patent: 6406950 (2002-06-01), Dakshina-Murthy
Wolf and Tauber, Silicon Processing for the VSLI Era, vol. 1, 2nd ed., , Lattice Press, 2000, pp. 245-247, 740-1,826-7.

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