Method for forming isolation region of semiconductor device

Details Method for forming isolation region of semiconductor device Method for forming isolation region of semiconductor device

1999-11-18

2000-09-26

Chaudhari, Chandra

Semiconductor device manufacturing: process

Formation of electrically isolated lateral semiconductive...

Grooved and refilled with deposited dielectric material

438225, 438425, H01L 2176

Patent

active

061241849

ABSTRACT:
A method for forming an isolation region of a semiconductor device includes the steps of forming first and second insulating layers on a substrate, removing the second insulating layer over an isolation region, forming an oxide layer by oxidizing the first insulating layer over the isolation region, forming sidewall spacers at sides of the second insulating layer and over the isolation region, forming a trench by etching the oxide layer and the substrate at the isolation region, removing the sidewall spacers, forming a third insulating layer on the substrate in the trench, and forming an isolation layer in the trench.

REFERENCES:
patent: 5173436 (1992-12-01), Gill et al.
patent: 5747376 (1998-05-01), Lee
patent: 5861339 (1999-01-01), Lien
patent: 5910018 (1999-06-01), Jang
K. Ishimaru et al., Trench Isolation Technology with 1.mu. m Depth n-and p-wells for A Full-CMOS SRAM Cell with a 0.4 .mu.m n .sup.+ /p.sup.+ Spacing, 1994 Symposium on VLSI Technology Digest of Technical Papers, pps. 97-98.

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