Semiconductor device manufacturing: process – Formation of electrically isolated lateral semiconductive... – Grooved and refilled with deposited dielectric material
Reexamination Certificate
2006-06-27
2006-06-27
Everhart, Caridad (Department: 2891)
Semiconductor device manufacturing: process
Formation of electrically isolated lateral semiconductive...
Grooved and refilled with deposited dielectric material
C438S756000, C438S737000
Reexamination Certificate
active
07067390
ABSTRACT:
Disclosed is a method for forming an isolation layer of a semiconductor device. The method includes the steps of providing a semiconductor substrate having a predetermined isolation region, sequentially forming a pad oxide layer and a pad nitride layer exposing the predetermined isolation region on the semiconductor substrate, forming a trench through etching the semiconductor substrate by a predetermined thickness using the pad nitride layer as a mask, forming a wall oxide layer at a side wall of the trench, sequentially forming a nitride layer and an oxide layer on a trench structure including the wall oxide layer, forming an Al2O3layer on an entire surface of a resultant structure, planarizing the Al2O3layer through polishing the Al2O3layer, and forming the isolation layer by removing the pad nitride layer.
REFERENCES:
patent: 6861334 (2005-03-01), Raaijmakers et al.
patent: 2002/0102814 (2002-08-01), Olsen
patent: 2002/0117731 (2002-08-01), Kim et al.
patent: 2003/0015764 (2003-01-01), Raaijmakers et al.
Ji Yun Hyuck
Kim Su Ho
Everhart Caridad
Hynix / Semiconductor Inc.
Ladas & Parry LLP
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