Active solid-state devices (e.g. – transistors – solid-state diode – Integrated circuit structure with electrically isolated... – Including dielectric isolation means
Reexamination Certificate
2005-12-27
2005-12-27
Trinh, Michael (Department: 2822)
Active solid-state devices (e.g., transistors, solid-state diode
Integrated circuit structure with electrically isolated...
Including dielectric isolation means
C257S510000, C257S647000
Reexamination Certificate
active
06979876
ABSTRACT:
A method for forming an isolation layer of a semiconductor device which is capable of improving isolation characteristics of a highly integrated semiconductor device. The method includes the steps of forming a first insulating layer on a substrate; forming both a first recess in the first isolation region and a plurality of second recesses in the second isolation region by only once applying a photolithography process to the first insulating layer; forming a third recess, which is deeper than the first recess, in the center area of the first recess in the first isolation region; and filling the first, second, third recesses with insulating materials or a thermal oxide layer. In addition, in the semiconductor device includes isolation regions have different widths, wherein the first isolation region, which is relatively narrower in width than the second isolation region, has a deeper recess than the second isolation region.
REFERENCES:
patent: 4390393 (1983-06-01), Ghezzo et al.
patent: 4396460 (1983-08-01), Tamaki et al.
patent: 4472240 (1984-09-01), Kameyama
patent: 4491486 (1985-01-01), Iwai
patent: 4492008 (1985-01-01), Anantha et al.
patent: 4609934 (1986-09-01), Haskell
patent: 4876214 (1989-10-01), Yamaguchi et al.
patent: 4962064 (1990-10-01), Haskell
patent: 4994406 (1991-02-01), Vasquez et al.
patent: 5015602 (1991-05-01), Van Der Plas et al.
patent: 5041898 (1991-08-01), Urabe et al.
patent: 5112772 (1992-05-01), Wilson et al.
patent: 5298450 (1994-03-01), Verret
patent: 5316966 (1994-05-01), Van Der Plas et al.
patent: 5371036 (1994-12-01), Lur et al.
patent: 5465003 (1995-11-01), Lur et al.
patent: 5474953 (1995-12-01), Shimizu et al.
patent: 5665616 (1997-09-01), Kimura et al.
patent: 5747377 (1998-05-01), Wu
patent: 5817567 (1998-10-01), Jang et al.
patent: 5893744 (1999-04-01), Wang
patent: 5895253 (1999-04-01), Akram
patent: 5899727 (1999-05-01), Hause et al.
patent: 5937311 (1999-08-01), Nagatomo
Hynix / Semiconductor Inc.
Trinh Michael
LandOfFree
Method for forming isolation layer of semiconductor device does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method for forming isolation layer of semiconductor device, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method for forming isolation layer of semiconductor device will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3496277