Semiconductor device manufacturing: process – Formation of electrically isolated lateral semiconductive... – Grooved and refilled with deposited dielectric material
Reexamination Certificate
2000-04-03
2001-05-22
Le, Vu A. (Department: 2824)
Semiconductor device manufacturing: process
Formation of electrically isolated lateral semiconductive...
Grooved and refilled with deposited dielectric material
C438S400000, C438S450000, 43, C257S050000
Reexamination Certificate
active
06235609
ABSTRACT:
FIELD OF INVENTION
The present invention is generally directed to the manufacture of a semiconductor device. In particular, the present invention relates to a process that enables the formation of isolation oxide above shallow isolation trench structures.
BACKGROUND OF INVENTION
One important stage in the manufacture of semiconductor devices is the formation of isolation areas to electrically separate the active devices or portions thereof, that are closely integrated in the silicon wafer. The particular structure of a given active device can vary between device types, a MOS-type transistor generally includes source and drain regions and a gate electrode that modulates current flowing in a channel between the source and drain regions. Unintended current should not flow between source and drain regions of adjacent MOS-type transistors. However, during the manufacturing process, movement of dopant atoms, for example, of boron, phosphorus, arsenic, or antimony, can occur within the solid silicon of the wafer. This movement is referred to as diffusion. The diffusion process occurs at elevated temperatures where there is a concentration gradient between dopant atoms external to the silicon wafer and those dopant atoms within the silicon wafer.
It is typically employed when forming p-type and n-type regions of a silicon integrated circuit device.
A technique referred to as “trench isolation” has been used to limit such flow. A particular type of trench isolation is referred to as shallow trench isolation (STI). STI is often used to separate the respective diffusion regions of devices of the same or different polarity type (i.e., p-type versus n-type). The trench regions are formed in the semiconductor substrate by recessing the substrate deep enough for isolation and refilling with insulating material to provide the isolation among active devices or different well regions.
In a conventional process, a significant problem with STI is that isolation oxide is exposed to numerous etch and clean sequences during subsequent processing, leading to recessing of the trench oxide. Excessive trench oxide loss may lead to inverse narrow width effects, excessive topography, and photo-alignment problems, excessive leakage on trench sidewalls and isolation breakdown. Consequently, device quality and reliability may be impaired.
Refer to
FIG. 1. A
cross-section of an STI structure
100
is built with a prior art process. The shallow trenches
120
in the silicon substrate
110
have received a fill oxide
130
. However, subsequent processing of the structure
100
has contributed to oxide recessing
140
. Oxide recessing
140
degrades the performance of the transistor active area
150
.
Accordingly, a need exists for a shallow trench isolation process that lessens the loss of trench oxide as the process technology approaches fractional microns.
SUMMARY OF INVENTION
The present invention is exemplified in a number of implementations, two of which is summarized below. A modification of a shallow trench isolation process enables the deposition of a wider oxide above the STI opening. The extra oxide width minimizes recessing along the trench sidewalls during subsequent wafer processing. In accordance with an embodiment of the invention a method for forming shallow trench isolation regions on a silicon substrate having a buffer oxide thereon and a nitride layer on top of the buffer oxide, comprises defining a mask layer on the nitride layer patterning isolation regions in unmasked areas of the nitride layer. Next, unmasked areas of the nitride and buffer oxide layers are etched until the silicon substrate is exposed. To form STI regions, further etching into the silicon substrate is done. According to the invention, providing a wider oxide above the STI opening involves performing a shaving of the nitride layer under the mask layer undercutting a portion of the nitride layer. After the nitride shaving, the mask layer is removed. An additional feature of this embodiment is that the shallow trench regions are filled in with a dielectric layer and this dielectric layer is planarized until it is substantially flush with the nitride layer. The dielectric layer may also be silicon oxide. The silicon oxide may be planarized by chemical mechanical polishing.
In accordance with another embodiment of the invention a method for forming shallow trench isolation regions on a silicon substrate having a buffer oxide thereon and a nitride layer on top of the buffer oxide, comprises defining a mask layer on the nitride layer patterning isolation regions in unmasked areas of the nitride layer. Next, unmasked areas of the nitride and buffer oxide layers are etched until the silicon substrate is exposed. To form STI regions of sufficient depth, further etching into the silicon substrate is done. This embodiment of the invention of providing a wider oxide above the STI opening involves performing a shaving of the mask layer over the nitride layer laterally trimming a portion of the mask layer exposing additional area of the nitride layer. After the mask layer shaving, the additional area of the nitride layer is etched until underlying buffer oxide is exposed. Next, the unshaved mask layer is removed. An additional feature of this embodiment is that the shallow trench regions are filled in with a dielectric layer and this dielectric layer is planarized until it is substantially flush with the nitride layer. Also the dielectric layer may be silicon oxide. Chemical mechanical polishing may be used to planarize the silicon oxide.
The above summaries of the present invention are not intended to represent each disclosed embodiment, or every aspect, of the present invention. Other aspects and example embodiments are provided in the figures and the detailed description that follows.
REFERENCES:
patent: 5410176 (1995-04-01), Liou et al.
patent: 5436190 (1995-07-01), Yang et al.
patent: 5981354 (1999-11-01), Spikes et al.
Nouri Faran
Sengupta Samit
Le Vu A.
Luu Pho
Philips Electronics North America Corp.
Zawilski Peter
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