Method for forming ion-implanted self-aligned gate structure by

Details Method for forming ion-implanted self-aligned gate structure by Method for forming ion-implanted self-aligned gate structure by

1977-10-21

1979-04-17

Rutledge, L. Dewayne

Metal treatment

Compositions

Heat treating

357 23, 357 59, 357 91, H01L 21265, H01L 754

Patent

active

041499042

ABSTRACT:
A method of manufacturing a silicon gate MIS device using ion implantation and controlled ion scattering to provide concurrent formation and automatic alignment of the gate structure and adjacent impurity regions. In a preferred embodiment, the process is for the gate structure and source and drain of silicon gate FETs. The layered gate constituents--typically oxide and silicon--are formed on a semiconductor wafer. A photoresist mask which is larger than the desired gate size is formed on the silicon and the silicon is etched to the predetermined gate size beneath the overhanging mask. The photoresist mask is then used during ion implantation of the source and drain to establish the lateral surface boundaries within which ions are implanted. These lateral surface boundaries are selected so that as the ions are driven into the substrate to the desired junction depth of the source and drain by lateral scattering, the source and drain are aligned with the silicon gate electrode.

REFERENCES:
patent: 3748187 (1973-07-01), Aubuchon et al.
patent: 3808058 (1974-04-01), Henning
patent: 3863330 (1975-02-01), Kraybill et al.
patent: 4060427 (1977-11-01), Barile et al.
Dennard et al., ". . . Short-Channel FET Device," IBM-TDB, 18 (1976) 2743.
Poponiak et al, "Forming Dielectric Isolation," IBM-TDB, 20 (1977) 1405.
Fang et al., "Forming Double Diffused Regions", IBM-TDB, 14 (1972) 3363.
Grant et al. ". . . Lateral Spread . . . Ions . . . into Si" Radiation Effects, vol. 29 (1976) pp. 189-190.

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