Method for forming interconnect in integrated circuits

Details Method for forming interconnect in integrated circuits Method for forming interconnect in integrated circuits

1995-04-07

1997-01-21

Tsai, H. Jey

Fishing, trapping, and vermin destroying

437 46, 437193, 437200, H01L 2128

Patent

active

055959350

ABSTRACT:
A structure and method for fabricating intergrated circuit which provides for the detection of residual conductive material. A first conductive layer is deposited over the intergrated circuit and patterned to define a first interconnect layer. An insulating layer in then formed over the integrated circuit. A second conductive layer is then deposited and patterned to define a second interconnect layer. Residual conductive material can be formed during pattering of the second interconnect layer when portions of the second conductive layer remain adjacent to the vertical sidewalls of the first interconnect layer. To make the residual conductive material easier to detect, the conductivity of the residual conductive material is increased by either implanting impurities into the integrated circuit or siliciding the residual conductive material with a refractory metal.

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