Method for forming integrated circuits bearing polysilicon of re

Details Method for forming integrated circuits bearing polysilicon of re Method for forming integrated circuits bearing polysilicon of re

1984-06-21

1985-12-24

Hearn, Brian E.

Metal treatment

Barrier layer stock material, p-n type

148 333, 148 15, 428620, H01L 2972

Patent

active

045604223

ABSTRACT:
A method for fabricating polysilicon of reduced resistance that may be incorporated in silicon integrated chip manufacturing processes which comprises coating a wafer bearing dielectrically isolated islands with an isolating layer, and depositing thereover a layer of polysilicon. On the surface of the polysilicon layer, a masking layer is formed, and coated with a metallic reflective layer. The portion of the reflective layer, and, optionally, the masking layer, overlaying the interisland area is removed, and the wafer is then exposed to a laser beam, transforming the polysilicon layer into the appropriate resistor material. The remaining metallic and/or masking layer may then be removed, the device exposed to a laser beam again, thereby transforming the polysilicon across the entire surface.

REFERENCES:
patent: 3953255 (1976-04-01), Combs, Jr.
patent: 4287526 (1981-09-01), Sakuma
patent: 4292091 (1981-09-01), Togei
patent: 4393573 (1983-07-01), Kato et al.
patent: 4475955 (1984-10-01), Patel

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