Semiconductor device manufacturing: process – Chemical etching
Reexamination Certificate
2001-08-17
2003-04-15
Utech, Benjamin L. (Department: 1765)
Semiconductor device manufacturing: process
Chemical etching
C438S694000, C438S702000, C438S706000, C438S737000, C438S738000
Reexamination Certificate
active
06548406
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method for forming an integrated circuit, and more particularly to a method for forming an integrated circuit having metal-oxide nitride-oxide semiconductor (MONOS) memories and mixed-signal circuits.
2. Description of the Related Art
In view of the demand of high integration and various applications of modern semiconductor devices, system on a chip (SOC) devices have been widely introduced, in which many devices having various functions such as logic devices and memory devices are integrated into one chip so that they interactively operate. Owing to the various different processes for forming logic devices such as metal oxide semiconductor (MOS)devices and memory devices such as non-volatile memory devices, it is much complicated and difficult to manufacture SOC devices having logic devices and memory devices. In order to integrate two or more different kinds of devices separately having different functions into one chip, it is necessary to develop processes that are compatible for various devices.
An embedded memory logic (EML) device, which is a type of SOC device, is obtained by integrating memory devices and logic devices into one chip. A whole EML device is a combination of a cell array region and a logic circuit region. Usually, a plurality of memory cells are located in the cell array region and data stored in the cell array region are computed or operated by the logic circuit. Typical memory cells such as DRAM cells, SRAM cells are widely used.
However, non-volatile memory cells such as NROM (Nitride Read-Only Memory) cells or MONOS memory cells are rarely integrated into SOC devices.
FIG. 1A
shows a MONOS memory cell fabricated on a substrate
100
. In
FIG. 1A
, an oxide layer
102
, a nitride layer
104
and an oxide layer
106
comprise an ONO (Oxide-Nitride-Oxide) layer. A polysilicon layer
108
used as the “metal” of the MONOS are also in FIG.
1
A.
FIG. 1B
shows a MOS device formed on a substrate
120
. The MOS device comprises a gate oxide layer
122
, a polysilicon gate electrode
124
and source/drain regions
126
a
and
126
b
.
FIG. 1C
shows a PIP (Polysilicon-Insulator-Polysilicon )capacitor formed on a substrate
130
, wherein the PIP capacitor comprises an oxide layer
132
, a polysilicon electrode
134
, an oxide layer
136
used as the insulator and a polysilicon gate
138
. MOS devices and PIP capacitors can constitute a mixed-signal circuit. It is noted that the MONOS device, the MOS device and the PIP capacitor have not only distinct structures and operating principles from each other, but also different process steps. In view of the various demands of manufacturing SOC devices such as reducing the production cost, integrating various process steps and upgrading the yield ratio, it is necessary to provide an improved process integration technology to meet the requirements of modern SOC manufacture. It is toward this goal that the invention especially directs.
SUMMARY OF THE INVENTION
It is therefore an object of the invention to provide a new process integration technology that can integrate MONOS devices, MOS devices and PIP capacitors into SOC devices.
It is another object of this invention to provide a method for forming SOC devices comprising MONOS devices, MOS devices and PIP capacitors with reduced process steps.
It is a further object of this invention to provide a method for forming SOC devices with reduced production cost, integrated process steps and upgraded yield ratio.
To achieve these objects, and in accordance with the purpose of the invention, the invention uses a method comprising: providing a substrate having an array region having a first dielectric layer, a second dielectric layer and a third dielectric layer stacked in sequence and a periphery region having said first dielectric layer thereon; forming a first conductive layer; forming a photoresist layer over said array region; implanting dopant ions into said first conductive layer; removing said photoresist layer; patterning to etch said first conductive layer to form a second conductive layer and a third conductive layer on said periphery region; removing said third dielectric layer to expose said second dielectric layer and said exposed first dielectric layer on said periphery region to expose said substrate; oxidizing said second dielectric layer, said substrate, said second conductive layer and said third conductive layer to form a fourth dielectric layer therein; forming a fourth conductive layer over said fourth dielectric layer; and patterning to etch said fourth conductive layer to a fifth conductive layer on said array region and a sixth conductive layer on said fourth dielectric layer and said third conductive layer. Said substrate can also has an array region having a first dielectric layer, a second dielectric layer and a third dielectric layer stacked in sequence and a periphery region having a dielectric layer thereon. The dielectric layer can be formed on the periphery region after etching the first dielectric layer, the second dielectric layer and the third dielectric layer.
The invention integrates non-volatile memory devices such as a MONOS device and a logic device such as a MOS device as well as a PIP capacitor into a SOC device with reduced process steps. The invention uses the first dielectric layer comprising a silicon dioxide layer as the first oxide layer of the MONOS device, the gate oxide layer of the MOS device and the bottom insulating layer of the PIP capacitor, thereby reduces the process steps. Moreover, the invention utilizes the first conductive layer comprising a polysilicon layer as the gate electrode of the MOS device and the resistor poly (RPOLY) of the PIP capacitor, and an N-type implantation or P-type implantation to adjust the conductivities of the gate electrode and the RPOLY at the same time. Thus less process steps are needed. Furthermore, the invention uses an oxidation process which is not sensitive to the substrate to form the top oxide layer of the MONOS and the insulating layer of the PIP capacitor, thereby avoid any reliability problem resulting from the etching damages of the third dielectric layer and leakage current resulting from the contact of the second dielectric layer and the fourth conductive layer, meanwhile, form the fourth dielectric layer used as the insulating layer of the PIP capacitor. The oxidation process which is not sensitive to the substrate can also be used to reoxidiz the polysilicon gate of the MOS device to reduce the leakage current. The invention also utilizes the fourth conductive layer to form the fifth conductive layer used as the metal of the MONOS device and the sixth conductive layer used as the GPOLY of the PIP capacitor, therefore the processes used to individually form the metal of the MONOS device and the GPOLY of the PIP capacitor are integrated and reduced.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the invention, as claimed.
REFERENCES:
patent: 5008214 (1991-04-01), Redwine
patent: 5364813 (1994-11-01), Koh
patent: 5591664 (1997-01-01), Wang et al.
patent: 5705438 (1998-01-01), Tseng
patent: 5731130 (1998-03-01), Tseng
patent: 5766994 (1998-06-01), Tseng
patent: 6417047 (2002-07-01), Isobe
patent: 6468865 (2002-10-01), Yang et al.
patent: 6468919 (2002-10-01), Chien et al.
patent: 2002/0136989 (2002-09-01), Lin
Chen Hsin-Huei
Chen Ying-Tso
Huang Yu-Ping
Hwang Shou-Wei
Lai Erh-Kun
Macronix International Co. Ltd.
Perez-Ramos Vanessa
Utech Benjamin L.
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