Semiconductor device manufacturing: process – Making passive device – Trench capacitor
Reexamination Certificate
2001-09-28
2003-09-16
Thomas, Tom (Department: 2811)
Semiconductor device manufacturing: process
Making passive device
Trench capacitor
C438S391000, C438S243000, C438S248000
Reexamination Certificate
active
06620699
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to semiconductor devices, and more particularly to a deep trench inside nitride spacer for trench-sidewall vertical device DRAM cells.
2. Discussion of Prior Art
The development of trench-sidewall vertical device dynamic random access memory (DRAM) cells has revealed various problems. For example, trench-sidewall vertical device DRAM cells need space, therefore high-density cells have been difficult to achieve. Further trench-sidewall vertical device DRAM cells have been prone to bitline shorts.
Poor wordline-bitline yield in trench-sidewall vertical device DRAM cells has limited the study of cell concepts with respect to vertical array devices. In a trench-sidewall vertical device DRAM cell, wordlines run directly over the gate poly of the vertical device, which is buried in the top part of the trench. Since the wordline is typically about 30% narrower than the top width of the trench, the wordline does not cap the trench completely. Assuming a perfect wordline to deep trench alignment, even after the spacer is put in place the top of the vertical gate poly is unprotected and can contact the bitline contact.
Planar array device technologies include nitride spacers to protect the sidewall of the gate conductor line. The top deep trench width is typically larger than the gate conductor line width. Deep trench spacer formation includes a recess etch, a spacer deposition and etch and a poly refill and planarization. These steps are performed at the end of the deep trench method and the poly stud is planarized to the pad nitride level. Since there is another planarization step at the end of the isolation trench process, which consumes some pad nitride, the spacer nitride may become a part of the surface. Thus, the spacer nitride is stripped with the pad nitride strip. A refill and etchback process is needed to fill seams and voids.
These seams and voids become more problematic at smaller ground rules, as they degrade the integrity of the device, and may reduced the retention time of the trench capacitor, adversely impacting the performance of the device.
Therefore, a need exists for an inside nitride spacer for deep trench device DRAM cells which is conserved during device formation.
SUMMARY OF THE INVENTION
According to an embodiment of the present invention, a method is provided for forming an inside nitride spacer in a deep trench device DRAM cell. The method includes depositing an oxide liner in a trench etched from a semiconductor material, wherein the oxide lines abuts a pad nitride layer, a pad oxide layer under the pad nitride layer, and a recessed gate poly in the trench. The method further includes depositing a spacer material on the oxide liner, removing exposed portions of the oxide layer from the semiconductor, and depositing a poly stud material over the semiconductor wherein the spacer material is encapsulated in poly stud material. The method includes polishing the semiconductor to the top trench oxide layer, and etching the top trench oxide layer.
The method includes etching the spacer to below a top surface of the pad nitride prior to depositing the poly stud material.
Removing exposed portions of the oxide layer further comprises performing an ozone cleaning.
Etching the top trench oxide layer exposes the spacer. The method includes forming a wordline over the gate poly, and forming a gate conductor spacer adjacent to the wordline, having a width overlapping the spacer, wherein the spacer substantially prevents a bitline contact from contacting the gate poly material in the trench.
The spacer is conserved during a formation of active area components. The spacer material is deposited on the oxide liner at a depth in the semiconductor material and a height greater than the semiconductor material.
According to an embodiment of the present invention, a method is provided for forming an inside nitride spacer in a deep trench device DRAM cell. The method includes depositing an oxide liner in a trench etched from a semiconductor material, wherein the oxide abuts a pad nitride layer, a pad oxide layer under the pad nitride layer, and a recessed gate poly in the trench. The method further includes depositing a spacer material on the semiconductor, etching the spacer to below a top surface of the pad nitride, and performing an ozone cleaning to remove exposed portions of the oxide layer from the semiconductor. The method includes depositing a poly stud material over the semiconductor wherein the trench is filled with the poly stud material, polishing the semiconductor to the top trench oxide layer, and etching the top trench oxide payer.
Etching the top trench oxide layer exposes the spacer. The method includes forming a wordline over the gate poly, and forming a gate conductor spacer adjacent to the wordline, having a width overlapping the spacer, wherein the spacer substantially prevents a bitline contact from contacting the gate poly material in the trench.
The spacer is conserved during a formation of the active area. The spacer material is deposited on the oxide liner at a depth in the semiconductor material and a height greater than the semiconductor material.
According to an embodiment of the present invention, a deep trench vertical dynamic access memory semiconductor device is provided including an oxide liner in an upper portion of a trench, a vertical gate poly filling a portion of the trench, and a spacer, formed on the oxide liner prior to and conserved during an active area process, for preventing contact between the vertical gate poly and a bitline contact.
The spacer overlaps a gate conductor spacer according to a critical distance and an overlay tolerance.
REFERENCES:
patent: 6008104 (1999-12-01), Schrems
patent: 6339241 (2002-01-01), Mandelman et al.
E. Sahouria, Y. Granik, N. Cobb, and O. Toublan, “Full-Chip Process Simulation for Silicon DRC,” Technology Report, Mentor Graphics Corp., San Jose, CA (2000) pp. 1-4.*
H. Baumgartner, V. Fuenzalida, and I. Eisele, “Ozone Cleaning of the Si—SiO(2) System,” Applied Physics A, vol.43, (1987) pp. 223-226.*
Maki Suemitsu, Tetsuya Kaneko, and Nobut Miyamoto, “Low Temperature Silicon Surface Cleaning by HF Etching/Ultraviolet Ozone Cleaning (HF/UVOC) Method (I)—Optimization of the HF Treatment,” Jap. Jour. of Applied Phys., vol.28, No. 12, (1987) pp. 2421-2424.
Dev Prakash C.
Scholz Arnd
Infineon Technologies North America Corp.
Magee Thomas
Thomas Tom
LandOfFree
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