Semiconductor device manufacturing: process – Making passive device – Resistor
Reexamination Certificate
2000-09-14
2002-12-10
Smith, Matthew (Department: 2825)
Semiconductor device manufacturing: process
Making passive device
Resistor
C438S763000, C438S764000, C438S793000, C438S384000
Reexamination Certificate
active
06492240
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention generally relates to a method for forming a high resistance resistor in mixed signal integrated circuits (IC), and more particularly to a method for forming mixed signal IC with improved high resistance resistor by treating the surface of polysilicon layer.
2. Description of the Prior Art
Because resistors, particularly high resistance resistors, integrated into mixed signal IC (integrated circuits) are usually used in telecommunication applications, they have been used in the mixed signal IC for ADSL (Asymmetric Digital Subscriber Line) broadband service application in recent decades. The high resistance resistors can reduce power consumption in a standby state of the devices used in broadband applications.
A conventional method for forming the high resistance resistor in mixed signal IC is performed by implanting low dosage ions into polysilicon, and is set forth below and explained by reference to
FIGS. 1A
to
1
H.
Referring to
FIG. 1A
, a substrate
110
is provided with a P well
111
and an N well
112
formed therein. An isolation region
115
is formed by a conventional CVD (Chemical Vapor Deposition) process, as is shown in
FIG. 1B. A
portion of this polysilicon layer
120
is used for the bottom electrode of the capacitor on the isolation region
15
and another portion is used for the resistor on the N well
112
.
Then, a polysilicon layer
120
is deposited on the substrate
110
using a conventional CVD (Chemical Vapor Deposition) process, as is shown in
FIG. 1B. A
portion of this polysilicon layer
120
is used for the bottom electrode of the capacitor on the isolation region
15
and another portion is used for the resistor on the N well
112
.
Next, referring to
FIG. 1C
, a blanket ion-implantation
130
is performed to adjust the resistance of the polysilicon layer
120
. The implanted dopants may be phosphorous or boron. Because high resistance is needed in the circuits, the doping dosage of this implantation is relatively low compared with the electrode of the capacitor.
Referring to
FIG. 1D
, a resistor patterned photoresist layer
140
is formed on the polysilicon layer
120
to block the following blank implantation
131
step. Because this implantation step
131
is used to reduce resistance of the bottom electrode of the capacitor, the patterned photoresist layer
140
is used to prevent the resistor region in polysilicon layer
120
from the implantation
131
.
Then the patterned photoresist layer
140
is stripped, and the polysilicon layer
120
is annealed, as shown in FIG.
1
E. The annealing step follows the above implantation steps
130
and
131
such that dopants in the polysilicon layer
120
can diffuse uniformly, and the photoresist layer
140
has to be stripped before annealing.
Having finished the annealing step, a second photoresist layer
141
is deposited on the polysilicon layer
120
, as shown in FIG.
1
F. This photoresist layer
141
comprises two patterns, which one is resistor pattern over the N well
112
and another is bottom electrode pattern over the isolation region
115
. Then, the polysilicon layer
120
is etched by using the photoresist layer
141
as a mask to form a resistor
121
and a bottom electrode
123
of a capacitor, as shown in FIG.
1
G.
Referring to
FIG. 1H
, having finished the resistor
121
, a dielectric layer
118
and another polysilicon layer
125
are sequentially deposited on the bottom electrode
123
to form a capacitor. Moreover, a metal-oxide-semiconductor transistor
150
is formed in and on the P well
111
. The transistor
150
comprises source/drain regions
151
, source/drain extension regions
152
, a poly gate electrode
153
, a gate oxide layer
154
, and spacers
155
.
However, both out diffusion generated in the step of
FIG. 1E
or over-deepened implantation generated in the step of
FIG. 1C
reduce the resistor's quality and reliability.
SUMMARY OF THE INVENTION
In accordance with the present invention, a main object of this method is to form an improved high resistance resistor in mixed signal integrated circuits that substantially increases reliability and quality during the formulation of the resistor.
It is another object of this invention that the treated surface polysilicon layer prevents diffusion in the annealing step to obtain reliable resistor.
It is a further object of this invention the treated surface polysilicon layer prevents over-deepened implantation.
In one embodiment, a method for forming a high resistance resistor in mixed signal integrated circuits is provided. The method includes first providing a substrate. Then, a polysilicon layer is deposited on the substrate. As a key step of this invention, the surface of the polysilicon layer is treated using a plurality of gases to form a diffusion barrier layer on the polysilicon layer, wherein the gases comprise N
2
O, O
2
, NO, and N
2
. In this invention, two methods for forming this amorphous layer are provided, including one using a plasma treatment, and another using a rapid thermal process (RTP). Then, ions are implanted into the polysilicon layer to adjust the resistance of the polysilicon layer. Next, the polysilicon layer is annealed, and the polysilicon layer is patterned to form the resistor on the substrate.
REFERENCES:
patent: 5849627 (1998-12-01), Linn et al.
patent: 5939763 (1999-08-01), Hao et al.
patent: 6008120 (1999-12-01), Lee
patent: 6069063 (2000-05-01), Chang et al.
patent: 6114258 (2000-09-01), Miner et al.
patent: 6245616 (2001-01-01), Buchanan et al.
patent: 6222256 (2001-04-01), Matsuura et al.
patent: 363246830 (1988-10-01), None
patent: 402035769 (1990-02-01), None
Wang Shyan-Yhu
Wu Kun-Lin
Powell Goldstein Frazer & Murphy LLP
Rocchegiani Renzo N.
Smith Matthew
United Microelectronics Corp.
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