Semiconductor device manufacturing: process – Repair or restoration
Reexamination Certificate
2000-06-30
2002-03-12
Fourson, George (Department: 2823)
Semiconductor device manufacturing: process
Repair or restoration
C438S149000, C438S798000
Reexamination Certificate
active
06355493
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates generally to a method for making high-density integrated circuits ICs) and, more particularly, to a method for decreasing the fringing capacitance and increasing the speed-power product of such ICs.
BACKGROUND OF THE INVENTION
In the manufacture of ICs, it is desirable, in some cases, for the substrate of the ICs to be semi-insulating (ie., have very high resistivity). Such semi-insulating substrates advantageously decrease fringing capacitance and improve the speed-power product of p-n junctions built thereon. This, in turn, allows for closer spacing of p-n junctions and, hence, an increase in the density of active circuit devices that are built on the substrate.
The prior art describes various fabrication methods to produce an IC with a high resistivity substrate. Those methods are, however, disadvantaged by drawbacks related either to limitations of the particular substrate chosen or limitations of the fabrication process itself.
In a first group of methods for manufacturing semiconductor devices on low-conductivity substrate, the low conductivity substrates are first formed, and then semiconductor devices are fabricated thereon. The substrates used in such methods include: (1) gallium arsenide and other wide gap semiconductors, (2) sapphire, (3) pure silicon and (4) compensated silicon.
Surveying the methods used in conjunction with these substrates, gallium arsenide (GaAs) has been made semi-insulating by growing it under very high purity conditions or by doping it with chromium. Unfortunately, the process is not applicable for use with silicon.
As to item (2), sapphire, a high resistivity substrate is formed by growing an epitaxial silicon layer thereon. But silicon-on-sapphire integrated circuits are much more costly than silicon ICs.
Item (3), super-pure silicon, has high-resistivity (up to 2×10
5
Ohm cm at room temperature). While initially semi-insulating, the resistivity drops to about 100 Ohm cm due to the accumulation of contaminants and oxygen donors that occurs as semiconductor devices are fabricated on such silicon.
In yet another technique, gold (or platinum) is diffused into silicon to increase the resistivity thereof A drawback to this approach is that the diffused gold tends to contaminate semiconductor devices that are formed on the silicon.
In a second group of processes for manufacturing semiconductor devices on low-conductivity substrate, semi-conductor devices are at least partially fabricated on a substrate, and then the substrate is rendered semi-insulating. One way to do this is by irradiating the device/substrate followed by annealing. Typically, irradiating/annealing methods use irradiating particles having energies in the millions of electron-volts (MeV) range and use an annealing temperature that is in the range of 250° C. to 450° C. A survey of such prior art follows.
In U.S. Pat. No. 4,469,527, Sugano et al. use high-flux thermal neutron irradiation to reduce silicon substrate conductivity. The irradiation introduces disordered regions in the silicon surface layer. After irradiation, Sugano et al. use pulsed laser processing with surface melting to anneal the disordered regions. In the Sugano et al. process, the dielectric parts (gates, etc.) of semiconductor devices are fabricated after neutron irradiation and after pulsed annealing. As a consequence, low temperature SiO
2
growth processes must be used in order not to heal the radiation-induced defects in the substrate that provide the substrate with its high resistivity. In particular, Sugano et al. use plasma anodization to grow SiO
2
. Gate oxides produced by anodization tend to be of low quality. Moreover, neutron irradiation produces radioactive isotopes in the silicon substrates causing potentially dangerous radioactivity.
In U.S. Pat. No. 5,017,508, Dodt et al. use the irradiation/anneal process to control minority carrier lifetimes in power semiconductor devices of IGBT (insulated-gate-bipolar-transistor) type. In particular, high-energy electrons are introduced into the semiconductor device, which electrons displace silicon atoms from their normal lattice positions. The displaced atoms interact with the silicon or dopant atoms to form combinations of atoms having energy levels between the normal conduction and valence bands of silicon. These energy levels act as recombination centers, which reduce minority carrier lifetimes. Such control of minority carrier lifetime results in improved device characteristics. After irradiation, Dodt anneals the wafer/device to restore operability to fully-fabricated semiconductor devices.
In the power devices to which Dodt et al. is directed, current flows through the entire substrate. Consequently, in such devices, the substrate must not be rendered semi-insulating. To this end, Dodt et al. use relatively low dose irradiation, typically less then 10 Mrad, i.e. less than about 10
15
cm
−2
of MeV-range energy electrons. (The term “dose” refers to the amount of radiation, not the energy thereof.) Such a dose is insufficient to significantly reduce the silicon substrate resistivity.
In U.S. Pat. No. 4,201,598, Tanaka et al. use the basic irradiation/annealing steps described above to remove or heal undesirable changes in the insulating portion of a semiconductor device while keeping desirable changes in the semiconductor portion of the device. Typically, radiation-induced changes in materials properties are caused by atomic displacements. Subsequent annealing promotes the return of displaced atoms (i.e., defects) to their initial locations, thereby canceling the action of the radiation and restoring the initial properties of the materials.
Tanaka et al. uses an annealing temperature that is in a range of between 250° C. and 350° C. to anneal a dielectric portion (ie., glass), but not semiconductor portions. The Tanaka et al. process is not applicable to CMOS. In particular, a MOSFET comprises both dielectric and semiconductor portions, and both such portions must be healed (i.e., annealed) to recover the operability thereof. Since Tanaka et al. anneal only the dielectric portion, the technique cannot be used for CMOS devices.
In U.S. Pat. No. 5,292,672, Akiyama et al. use spatially localized control of properties of the semiconductor portions of the semiconductor device using proton irradiation. Accelerated protons cause atomic displacements in materials at a depth at which they lose their energy and stop. This depth is in the range of about 0.1 to 10 microns from the surface, as a function of the initial energy of the accelerated protons. The protons also slightly affect the insulator layers of the semiconductor device before coming to rest. Akiyama et al. use subsequent annealing to heal the insulator portions of the semiconductor device. The accelerated protons disadvantageously do not render the entire semiconductor substrate semi-insulating, such that benefits of a semi-insulating substrate are not obtained.
In U.S. Pat. No. 4,684,413, Goodman et al. uses the irradiation/annealing process to improve the switching speed of semiconductor devices. Irradiation is also used to reduce minority carrier lifetime in the semiconductor portions of the semiconductor device. Annealing is used to remove radiation-induced defects that have a low thermal stability within the temperature operating range of the semiconductor device. Without such annealing, the presence of the low thermal stability-type defects would change the characteristics of the operating device. Unfortunately, Goodman et al., like Tanaka et al., is not applicable to CMOS.
In U.S. Pat. No. 4,479,829, Kniepkamp irradiates gallium arsenide substrate/prefabricated semiconductor devices with electrons to render the substrate highly resistive. Kniepkamp is not, however, applicable to silicon-based structures. A second disadvantage of Kniepkamp's process is the use of pulsed laser annealing for localized annealing. Laser annealing has low efficiency as a method for localized annealing and it is also complicated.
In U.S. Pat. No
DeMont & Breyer
Fourson George
Pham Thanh V
Silicon Wafer Technologies Inc.
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