Method for forming hot-carrier suppressed sub-micron MISFET devi

Details Method for forming hot-carrier suppressed sub-micron MISFET devi Method for forming hot-carrier suppressed sub-micron MISFET devi

1991-02-14

1992-03-03

Hearn, Brian E.

Fishing, trapping, and vermin destroying

437 44, 437 46, 437189, 437191, 437913, 148DIG82, H01L 21265

Patent

active

050932756

ABSTRACT:
Hot-carrier suppression in a sub-micron MISFET structure is achieved by providing a drain region which includes a steeply profiled N+ (or P+) doped region in the surface of a semiconductor body with a first epitaxial layer formed thereover having N- (or P-) dopant concentration. A second N+ (or P+) epitaxial layer is formed over the first epitaxial layer and functions as a low ohmic contact to the drain region. In a preferred embodiment both the source and drain regions have dopant concentrations provided by N+ (or P+) doped regions in the surface of a substrate with epitaxial layers thereover. The dopant profile reduces the voltage drop across the more highly doped region of the drain and thereby reduces the electric field therein. Further, the reduction in dopant concentration reduces the electric field due to energy band bending associate with the change in doping level from the N+ (P+) region to the N- (P-) epitaxial layer. The resulting sub-micron device has better long-term reliability. The epitaxial layers are adjacent to and spaced from the gate contact by a dielectric layer such as silicon oxide. In a preferred embodiment, the dielectric layer is thicker between the second epitaxial layer and the gate contact than between the first epitaxial layer and the gate contact.

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