Metal fusion bonding – Process – Plural joints
Reexamination Certificate
2000-01-06
2001-04-17
Ryan, Patrick (Department: 1725)
Metal fusion bonding
Process
Plural joints
C228S121000, C228S123100, C029S599000, C438S002000, C438S119000, C438S614000, C438S708000, C438S725000, C427S062000, C427S123000, C427S126100
Reexamination Certificate
active
06216941
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to device interconnection techniques, and more specifically to a method for attaching high temperature superconductive (HTS) microelectronic chips (i.e., any substrate material onto which an HTS film is deposited) and similar fragile circuits directly to HTS substrates and similar fragile materials.
2. Description of the Prior Art
Rapid advances in technology have accelerated the need for device interconnections that can satisfy increased speed without compromising yield or reliability. Specifically, as the development of high temperature superconductive (HTS) electronics mature, the need for making high frequency connections to these HTS circuits becomes essential.
Conventional device interconnection techniques may include wire bonding, flip chip solder reflow bonding, or flip chip cold weld bonding. Flip-chip bonding tends to be particularly popular since microelectronic circuits having higher input/output densities may be fabricated, thereby allowing more functions to be incorporated in a single package. Unlike other conventional interconnect methods, flip-chip attachment provides interconnections that can operate at multi-GHz speeds.
However, conventional solder reflow and cold weld flip-chip bonding methods fail to address the mechanical fragility and chemical sensitivity of high temperature superconductive films and substrates. For example, in one method of flip-chip bonding known in the art as “cold weld” attachment, metal bumps are deposited on a surface of a device chip and on a surface of a substrate. The metal bumps of the chip are brought into contact with the corresponding metal bumps of the substrate where pressure is applied causing the metal bumps from the chip and the substrate to deform and flow together forming an electromechanical connection. However, this cold weld flip-chip bond method is unsuitable for HTS and similarly fragile chips. Specifically, HTS chips are composed of superconducting films that are epitaxially grown on structurally fragile substrate materials. Using conventional cold weld methods, HTS chips and substrates are vulnerable because the amount of pressure that is typically required for making a reliable electromechanical connection is greater than the HTS substrate material can withstand without fracturing.
Flip-chip bonding methods that utilize chemicals during the attachment process present additional problems because of the chemical sensitivity of HTS film layers. For example, in an alternative method of flip-chip bonding, a conductive pattern of bumps formed on a surface of a chip is mounted and mated to a corresponding pattern formed on the surface of a substrate by reflow soldering using heat and an oxide reducing chemical agent while applying pressure. Here, the amount of pressure typically applied is minimal and therefore the HTS substrate is not susceptible to fracture. However, the chemicals used to reduce oxide contaminants on the surface of the solder will destroy the HTS film.
Based on the techniques known in the art for bonding chips to substrates, a flip-chip bonding method that provides high bandwidth connections and strong metallurgical bonds while accommodating the chemical sensitivity of HTS films and the fragility of the substrate materials onto which the HTS films are deposited is highly desirable.
SUMMARY OF THE INVENTION
It is an aspect of the present invention to provide a method for forming high frequency connections between a chip and a substrate. The method includes the step of selectively depositing metal on a surface of the chip and the surface of the substrate to respectively form metal layers on the chip surface and the substrate surface. Selectively forming a pattern of electrically conductive bumps on the chip surface over the metal layer so that each electrically conductive bump forms a spongy and dendritic structure. Selectively forming a pattern of electrically conductive bumps on the substrate surface over the substrate metal layer such that each electrically conductive bump forms a spongy and dendritic structure, and the substrate bump pattern correspondingly matches the chip bump pattern. Placing the chip in aligned contact with the substrate where each electrically conductive chip bump mates with each corresponding electrically conductive substrate bump, and selectively applying heat and pressure to the chip and substrate causing each chip bump to fuse with each corresponding substrate bump to form an electromechanical bond.
REFERENCES:
patent: 5092032 (1992-03-01), Murakami
patent: 5773875 (1998-06-01), Chan
patent: 5977642 (1999-11-01), Appelt et al.
patent: 5986348 (1999-11-01), Fukano
patent: 6055723 (2000-05-01), Akerling et al.
Akerling Gershon
Sergant Moshe
Yokoyama Karen E.
Cooke Colleen
Ryan Patrick
TRW Inc.
Yatsko Michael S.
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