Method for forming high-density integrated circuit capacitors

Details Method for forming high-density integrated circuit capacitors Method for forming high-density integrated circuit capacitors

1999-01-27

2001-01-09

Kunemund, Robert (Department: 1765)

Semiconductor device manufacturing: process

Chemical etching

Vapor phase etching

C438S710000, C438S712000, C438S720000

Reexamination Certificate

active

06171970

ABSTRACT:

FIELD OF THE INVENTION
This invention relates to semiconductor integrated circuits, and more specifically to dynamic random access memory storage capacitors.
BACKGROUND OF THE INVENTION
Increasing demand for semiconductor memory and competitive pressures require higher density integrated circuit dynamic random access memories (DRAMs) based on one-transistor, one-capacitor memory cells. But scaling down capacitors with the standard silicon oxide and nitride dielectric presents problems including decreasing the quantity of charge that may be stored in a cell. Consequently, alternative dielectrics with dielectric constants greater than those of silicon oxide and nitride are being investigated. Various dielectric materials are available, such as tantalum pentoxide (dielectric constant about 25 versus silicon nitride's dielectric constant of about 7) as described in Ohji et al., “Ta
2
O
5
capacitors' dielectric material for Giga-bit DRAMs,” IEEE IEDM Tech. Dig. 5.1.1 (1995); lead zirconate titanate (PZT), which is a ferroelectric and supports nonvolatile charge storage (dielectric constant of about 1000), described in Nakamura et al., “Preparation of Pb(Zr,Ti)O
3
thin films on electrodes including IrO
2
, 65 Appl. Phys. Lett. 1522 (1994); strontium bismuth tantalate (also a ferroelectric) described in Jiang et al. “A New Electrode Technology for High-Density Nonvolatile Ferroelectric (SrBi
2
Ta
2
O
9
) Memories,” VLSI Tech. Symp. 26 (1996); and barium strontium titanate (dielectric constant about 500), described in Yamamichi et al., “An ECR MOCVD (Ba,Sr)TiO
3
based stacked capacitor technology with RuO
2
/Ru/TiN/TiSi
x
storage nodes for Gbit-scale DRAMs,” IEEE IEDM Tech. Dig. 5.3.1 (1995), Yuuki et al., “Novel Stacked Capacitor Technology for 1 Gbit DRAMs with CVD-(Ba,Sr)TiO
3
Thin Films on a Thick Storage Node of Ru,” IEEE IEDM Tech. Dig. 5.2.1 (1995), and Park et al., “A Stack Capacitor Technology with (Ba,Sr)TiO
3
Dielectrics and Pt Electrodes for 1 Giga-Bit density DRAM, VLSI Tech. Symp. 24 (1996). Also see Dietz et al., “Electrode influence on the charge transport through SrTiO
3
. thin films, 78 J. Appl. Phys. 6113 (1995), (describes electrodes of Pt, Pd, Au, and so forth on strontium titanate); U.S. Pat. No. 5,003,428 (PZT and barium titanate), U.S. Pat. No. 5,418,388 (BST, SrTiO
3
, PZT, etc.), and U.S. Pat. No. 5,566,045 (thin Pt on BST).
These alternative dielectrics are typically deposited at elevated temperatures and in an oxidizing ambient. Hence, an oxygen-stable bottom electrode material such as platinum or ruthenium oxide is used. Platinum exhibits the best leakage characteristics in capacitor structure and therefore is the subject of extensive study for integration into DRAM process flows. Platinum, however, readily forms a silicide when in direct contact with silicon, and further is not a good barrier to oxygen due to fast diffusion down the platinum grain boundaries. A further difficulty with platinum is that it has proven difficult to etch with a dry process. Such a dry process will be instrumental in achieving the wafer throughput necessary to justify integration of platinum into commodity products such as DRAMs.
Past dry etching efforts have focused on reactive ion etching (RIE) using chemistries that include argon, chlorine, SF
6
, and CF
4
. See C.E. Farrell, et al., “A Reactive Ion Etch Study for Producing Patterned Platinum Structures,” Integrated Ferroelectrics, vol. 16, pp. 109-138, 1997; and K. R. Milkove and C. X. Wang, “Analysis of a Fence-free Platinum Etch Process,” Integrated Ferroelectrics, vol. 17, pp. 403-419, 1997. These prior art processes have thus far achieved disappointing results. The challenge in this technology is to form platinum pedestals (bottom capacitor electrodes) having a height on the order of 0.3 um and a minimum lateral dimension of between 0.1 um and 0.2 um. The pitch between electrodes will also be on the order of the minimum feature size. To achieve the packing density and capacitance required in the 1 Gigabit DRAM generation and beyond, the sidewalls of the platinum bottom electrode will be between 80° and 90° relative to the surface on which the pedestal is formed. See FIG.
1
. The prior art processes mentioned above produce sidewall angles that are typically less than 40° using dry-etching only, and less than 70° when the dry etch is followed by a wet cleanup etch. Milkove and Wang, in “Insight into the dry etching of fence-free patterned platinum structures”, J. Vac. Sci. Technol. A 15(3), May/Jun 1997, pp. 596-603, attribute the shallow sidewall angles to a combination of fence formation on the photoresist mask and lateral mask erosion. The fence formation is a result of redeposited platinum, and is believed to be the dominant factor in determining sidewall angle.
SUMMARY OF THE INVENTION
In accordance with a preferred embodiment of the invention, there is disclosed a method for etching a platinum surface. The method includes the step of forming a hardmask including titanium, aluminum, and nitrogen on the platinum surface. The hardmask covers portions of the platinum surface. The method further includes removing platinum from uncovered portions of the surface with a plasma including a nitrogen-bearing species. The etch chemistry may also comprise an oxygen-bearing species.
In accordance with another preferred embodiment of the invention, there is disclosed a method for forming a capacitor electrode. The method includes the steps of forming a platinum layer on a substrate and forming a hardmask including titanium, aluminum, and nitrogen on the platinum layer. The hardmask covers portions of the platinum layer. The method also includes the step of etching uncovered portions of the platinum layer in a plasma etcher with a plasma including a nitrogen-bearing species. The etch chemistry may also comprise an oxygen-bearing species.
An advantage of the inventive concepts is that platinum, which has historically been difficult to pattern and etch, is capable of being etched to fine features and with steep sidewall profiles. The nitrogen in the etch chemistry combines with the hardmask to reduce erosion of the hardmask during etching of the platinum.


REFERENCES:
patent: 5477074 (1995-12-01), Yen
patent: 5591302 (1997-01-01), Shinohara et al.
patent: 5930639 (1999-07-01), Schuele et al.
patent: 5972722 (1999-10-01), Visokay et al.

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