Semiconductor device manufacturing: process – Chemical etching – Vapor phase etching
Reexamination Certificate
2000-08-08
2002-10-15
Nelms, David (Department: 2818)
Semiconductor device manufacturing: process
Chemical etching
Vapor phase etching
C438S709000
Reexamination Certificate
active
06465362
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method for fabricating a semiconductor device, and in particular to a method for forming a gate of a semiconductor device.
2. Background of the Related Art
As an integration technology of a semiconductor device is developed, a design rule thereof has become gradually stricter. In highly integrated devices with strict design rules, a delay of an operational speed of the device resulting from a high resistance of a gate becomes a serious problem. In order to solve such a problem, a polycide (i.e., silicide on doped polycrystalline silicon) gate electrode formed of a refractory metal silicide having a low resistance on a doped polycrystalline silicon has been generally used as a gate electrode. Currently, a popular material for the polycide is a tungsten silicide such as WSi
2
, which has a specific resistance of 60~200 &mgr;&OHgr;cm. Since an integration degree of the device has been increased, there is an increasing demand for a silicide having a lower resistance than the tungsten silicide. In regard to this, a cobalt silicide such as CoSi
2
, which has a specific resistance of 15~20 &mgr;&OHgr;cm and a titanium silicide such as TiSi
2
, which has a specific resistance of 15~20 &mgr;&OHgr;cm have been noted.
Both the cobalt silicide and the titanium silicide have a low specific resistance property between 15 and 20 &mgr;&OHgr;cm, and thus could replace the tungsten silicide. The cobalt silicide is superior to the titanium silicide in many respects. Superior properties of the cobalt silicide will now be described.
First, during an annealing step after forming the silicide, the silicide is agglomerated, and thus, a resistance thereof is increased. The agglomeration phenomenon occurs less in the cobalt silicide than in the titanium silicide. As a result, the cobalt silicide has better thermal stability than the titanium silicide.
Second, in the titanium silicide, as a width of a gate is decreased, a resistance thereof is significantly or remarkably increased. However, even when a width of a gate is narrow, a resistance of the cobalt silicide is maintained low.
Third, the cobalt silicide can dope the polycrystalline silicon by using a Silicide-As-Doping source (SADS) method. The SADS method is a doping method of the polycrystalline silicon that implants and anneals a dopant into the silicide, and diffuses the implanted dopant into the polycrystalline silicon therebelow. Here, the titanium silicide has a great reactivity with a dopant such as arsenic (As), phosphorous (P) and boron (B). Accordingly, the titanium silicide cannot be used in accordance with the SADS method. Conversely, the cobalt silicide has a small reactivity with the dopant, and thus, the SADS method can be employed.
Although having many advantages, the cobalt silicide is hard to adapt to the polycide. In the case of the titanium silicide, a volatile material such as TiF and TiCl
2
is generated according to a dry etching process, and thus, it is possible to perform an etching process for forming the polycide. However, cobalt (Co) composing the cobalt silicide is chemically stable, and thus, a corresponding volatile material such as TiF and TiCl
2
is rarely generated, differently from titanium (Ti). As a result, the cobalt silicide has a disadvantage in that it is difficult to carry out the etching process for forming the polycide.
In order to overcome the above-mentioned disadvantage for cobalt silicide, there has been employed a Damascent method of forming an insulation layer. The Damascent method operates by forming a hole by partially etching the insulation layer of an area where the cobalt silicide layer will be formed, forming the cobalt silicide layer in the hole, and removing the insulation layer. However, the Damascent method has complicated processes, and is difficult to perform a critical dimension (CD) control for forming the cobalt silicide layer to have a pattern of a desired size for highly integrated devices. Accordingly, the Damascent method cannot be practically used. As a result, a method of etching the cobalt silicide is needed to form the polycide using or consisting of the cobalt silicide.
The above references are incorporated by reference herein where appropriate for appropriate teachings of additional or alternative details, features and/or technical background.
SUMMARY OF THE INVENTION
An object of the invention is to solve at least the above problems and/or disadvantages and to provide at least the advantages described hereinafter.
An object of the present invention is to provide a method for fabricating a gate of a semiconductor device that substantially obviates one or more problems caused by disadvantages and limitations of the related art.
Another object of the present invention to provide a method for fabricating a polycide gate.
Another object of the present invention to provide a method for fabricating a polycide by using a cobalt silicide such as CoSi
2
which has various excellent properties.
In order to achieve at least the above-described objects in a whole or in parts of the present invention, there is provided a method for forming a gate of a semiconductor device, that includes a step of preparing a semiconductor substrate, a step of forming a first insulation layer on the semiconductor substrate, a step of forming a polycrystalline silicon layer doped simultaneously with deposition or after the deposition, a step of forming a cobalt silicide layer by deposition or by reacting a cobalt layer with the polycrystalline silicon layer, a step of patterning the cobalt silicide layer by using at least one etchant gas selected from a group of a gas including a chlorine atom group, a gas mixture of the gas including the chlorine atom group and oxygen, a gas mixture of the gas including the chlorine atom group and an inert gas, and a gas including the above-described gases and a gas having a fluorine atom group and a step of patterning the polycrystaline silicon layer.
To further achieve the above objects in a whole or in parts, there is provided a method of manufacturing a semiconductor device according to the present intention that includes providing a semiconductor substrate, forming a first insulation layer, a polycrystaline silicon layer and a cobalt silicide layer on the semiconductor substrate, patterning the cobalt silicide layer by using at least one etchant gas selected from the group consisting of a first gas including a chlorine atom group, a second gas being a mixture of the first gas and oxygen, a third gas being a mixture of the first gas and an inert gas, and a fourth gas being one of the first through third gases and a gas having a fluorine atom group, and patterning the polycrystalline silicon layer.
To further achieve the above objects in a whole or in parts, there is provided a method of manufacturing a semiconductor device according to the present intention that includes providing a semiconductor substrate, sequentially forming a first insulation layer, a polycrystalline silicon layer and a cobalt silicide layer on the semiconductor substrate, patterning the cobalt silicide layer by using at least one etchant gas including a chlorine atom group, and patterning the polycrystalline silicon layer to form a gate electrode.
Additional advantages, objects, and features of the invention will be set forth in part in the description which follows and in part will become apparent to those having ordinary skill in the art upon examination of the following or may be learned from practice of the invention.
The objects and advantages of the invention may be realized and attained as particularly pointed out in the appended claims.
REFERENCES:
patent: 5897349 (1999-04-01), Agnello
patent: 5914276 (1999-06-01), Shin et al.
patent: 6124212 (2000-09-01), Fan et al.
Chae Soo Doo
Yoo Kyoung Jin
Fleshner & Kim LLP
Hyundai Electronics Industries Co,. Ltd.
Le Dung A
Nelms David
LandOfFree
Method for forming gate of semiconductor device does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method for forming gate of semiconductor device, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method for forming gate of semiconductor device will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2980673