Semiconductor device manufacturing: process – Formation of electrically isolated lateral semiconductive... – Grooved and refilled with deposited dielectric material
Reexamination Certificate
2001-03-20
2002-07-09
Niebling, John F. (Department: 2813)
Semiconductor device manufacturing: process
Formation of electrically isolated lateral semiconductive...
Grooved and refilled with deposited dielectric material
C438S427000
Reexamination Certificate
active
06417073
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates to a method for forming an element isolating region in a semiconductor device and, more particularly to, a method for forming a Shallow Trench Isolation (STI) by filling with an insulator film a shallow trench in a surface of a semiconductor substrate.
The present application claims priority of Japanese Patent Application No. 2000-078773 filed on Mar. 21, 2000, which is hereby incorporated by reference.
2. Description of the Related Art
With improvements in fine patterning of semiconductor elements formed in a semiconductor silicon substrate, it has been difficult for a method for forming element isolating regions by use of a conventional LOCal Oxidation of Silicon (LOCOS) method to form accurately an active region having a width in an order of 0.1 &mgr;m or less, thus being mainly replaced by an STI method.
FIGS. 7A
to
7
E are schematically cross-sectional views for illustrating conventional steps of forming an element isolating region. As can be seen from
FIGS. 7A
to
7
E, a conventional STI is formed as follows.
First, a pad oxide film
302
is formed on a silicon substrate
301
by thermal oxidation. A silicon nitride film
303
is formed which covers the pad oxide film
302
. The portions of the silicon nitride film
303
and the pad oxide film
302
which exist on a formation-reserved element isolating region are patterned sequentially by anisotropic etching. By conducting anisotropic etching on the silicon substrate
301
using the silicon nitride film
303
as a mask, shallow trenches
305
are formed in the formation-reserved element isolating region on the surface of the silicon substrate
301
.
Next, a thermal oxide film
307
is formed on the surface of the trenches
305
by thermal oxidation.
High-Density Plasma-Enhanced CVD (HD-PECVD) accompanied by bias sputtering is conducted to form a silicon oxide film
311
throughout on the surface to a predetermined film thickness to thereby fill and cover the trenches
305
completely with the silicon oxide film
311
(see FIG.
7
A).
Next, Chemical Mechanical Polishing (CMP) is conducted (using the silicon nitride film
303
as a stopper) on the silicon oxide film
311
until an upper surface of the silicon nitride film
303
is exposed, to leave a silicon oxide film
311
a
in the trenches
305
(see FIG.
7
B).
Next, etching-back is conducted on the silicon oxide film
311
a
using buffered hydrofluoric acid (BHF) to leave a silicon oxide film
311
b
in the trenches
305
. At this point in time, an upper surface of the silicon oxide film
311
b
roughly agrees in level with an upper surface of the pad oxide film
302
in level (see FIG.
7
C).
Next, for example, wet etching by use of hot phosphoric acid is conducted on the silicon nitride film
303
to remove it (see FIG.
7
D).
Subsequently, the silicon oxide film
311
b
and the pad oxide film
302
are removed by wet etching by use of hydrofluoric acid (e.g., buffered hydrofluoric acid). With this, portions of a surface of the silicon substrate
301
which are expected to be an active region (element forming region) are exposed to leave a silicon oxide film
311
c in the trenches
305
, thus completing the conventional STI (see FIG.
7
E).
The above-mentioned conventional STI forming method, however, may generate a fine scratch (hereinafter called micro-scratch)
315
in the surface of the silicon oxide film
311
a
as a result of CMP conducted thereon (see FIG.
7
B). The micro-scratch
315
may sometimes measure about 0.1 &mgr;m to 100 &mgr;m in length.
Further, since after the trenches
305
are formed it is difficult to avoid etching the pad oxide film
302
during cleaning before the thermal oxide film
307
is formed, an under-cut is liable to be formed at the ends of the silicon nitride film
303
. Accordingly, when the silicon oxide film
311
is formed, density of the silicon oxide film
311
may decrease in vicinity of a lower edge of an end of this silicon nitride film
303
, thus further generating a void (not shown).
If the silicon oxide film
311
a
is anisotropically etched with buffered hydrofluoric acid with a presence of the micro-scratch
315
, the micro-scratch
315
expands anisotropically. When, in this case, the micro-scratch
315
comes near the lower edge of the end of the above-mentioned silicon nitride film
303
, etching of the silicon oxide film
311
rapidly spreads from there as a center to all around a belonging element forming region, to form a notch shape (hereinafter called debot
316
) in the silicon oxide film
311
b
around that element forming region (see FIG.
7
C). This debot
316
further develops to provide a debot
316
a
during wet-etching in which the silicon oxide film
311
c
is left (see FIG.
7
E).
Thus, the conventional STI forming method suffers from a problem that width of a specific element forming region becomes larger than its design value all over its peripheries. If a semiconductor device has MOS transistors therein, such a transistor MOS may be formed that has, for example, an extremely increased reverse narrow channel effect, thus deteriorating the electric characteristics of the MOS transistor. Also, in patterning of gate electrodes in post-steps, etch residues of a conductive film may be induced at the debot
316
a.
SUMMARY OF THE INVENTION
In view of the above, it is an object of the present invention to provide a method for forming an STI to suppress an effective expansion of an element forming region. It is another object of the invention to provide a method for forming the STI easy to suppress an increase in a reverse channel effect, deterioration of electric characteristics, and induction of etch residues of gate electrodes in a post-step in some transistors in a semiconductor device containing MOS transistors. It is further another object of the invention to provide a method for forming the STI easy to suppress an occurrence of the debot even when the micro-scratch is present.
According to a first aspect of the present invention, there is provided a method for forming an element isolating region, including the steps of:
forming a pad oxide film on a surface of a silicon substrate by thermal oxidation and forming a silicon nitride film which covers the pad oxide film and then conducting anisotropic etching sequentially on portions of the silicon nitride film and the pad oxide film which exist on a formation-reserved element isolating region to then conduct anisotropic etching using the silicon nitride film as a mask in order to form a trench in a surface of the silicon substrate, thus forming a first silicon oxide film throughout on the surface by High-Density Plasma-Enhanced CVD (HD-PECVD) accompanied by bias sputtering;
conducting Chemical Mechanical Polishing (CMP) on the first silicon oxide film until a surface of the silicon nitride film is exposed;
forming by spin coating or liquid-phase deposition a second silicon oxide film which covers a surface of the silicon nitride film and a surface of the first silicon oxide film to thereby conduct heat treatment in an oxygen atmosphere, serving also to refine the second silicon oxide film;
conducting such anisotropic etching using an etching gas that an etching rate for the silicon oxide film may be equal to an etching rate for the silicon nitride film to thereby remove the second silicon oxide film in order to remove the silicon nitride film and the first silicon oxide film; and
remove by wet etching the pad oxide film, and the first silicon oxide film until at least the surface of the silicon substrate is exposed.
In the foregoing first aspect, a preferable mode is one wherein the second silicon oxide film is formed by spin coating and consists of an inorganic SOG (Spin-On-Glass) film made of silicon hydride sesqui-oxide (HSiO
3/2
) n as a material.
According to a second aspect of the present invention, there is provided a method for forming an element isolating region, including the steps of:
forming a pad oxide film on a surface of a silicon substrate by thermal oxid
Blum David S
Hayes & Soloway P.C.
NEC Corporation
Niebling John F.
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