Method for forming device-isolating layer in semiconductor devic

Semiconductor device manufacturing: process – Formation of electrically isolated lateral semiconductive... – Grooved and refilled with deposited dielectric material

Patent

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

438424, 438427, 438437, 148DIG50, H01L 2176

Patent

active

060339705

ABSTRACT:
A method for forming a device-isolating layer of a semiconductor device in which an APCVD oxide layer and an HDPCVD oxide layer are successively deposited to fill trenches. The method includes forming a thermal oxide layer on a semiconductor substrate including active regions and device-isolating regions, forming a nitride layer on the thermal oxide layer, selectively etching the nitride layer to be removed over the device-isolating regions and selectively etching the thermal oxide layer and the semiconductor substrate with the patterned nitride layer serving as a mask to form trenches. The method further includes forming another thermal oxide layer on the surface of the trenches, forming an APCVD oxide layer on the entire surface including the thermal oxide layer and the patterned nitride layer, forming and annealing an HDPCVD oxide layer on the entire surface of the APCVD oxide layer to fill the trenches. The HDPCVD oxide layer is then polished using a CMP process. However, the HDPCVD oxide layer remains in the trenches.

REFERENCES:
patent: 5498565 (1996-03-01), Gocho et al.
patent: 5702977 (1997-12-01), Jang et al.
patent: 5731241 (1998-03-01), Jang et al.
patent: 5741740 (1998-04-01), Jang et al.
patent: 5851899 (1998-12-01), Weigand
patent: 5880007 (1999-03-01), Varian et al.
Jun. 18-20, 1996 VMIC Conference 1996 ISMIC-106/96/0063(c), "Evaluation of Cyclotene.TM. 5021 as a Low Dielectric Constantild" pp. 63-68.

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Method for forming device-isolating layer in semiconductor devic does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method for forming device-isolating layer in semiconductor devic, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method for forming device-isolating layer in semiconductor devic will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-362489

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.