Semiconductor device manufacturing: process – Formation of electrically isolated lateral semiconductive... – Grooved and refilled with deposited dielectric material
Patent
1998-06-24
2000-03-07
Dang, Trung
Semiconductor device manufacturing: process
Formation of electrically isolated lateral semiconductive...
Grooved and refilled with deposited dielectric material
438424, 438427, 438437, 148DIG50, H01L 2176
Patent
active
060339705
ABSTRACT:
A method for forming a device-isolating layer of a semiconductor device in which an APCVD oxide layer and an HDPCVD oxide layer are successively deposited to fill trenches. The method includes forming a thermal oxide layer on a semiconductor substrate including active regions and device-isolating regions, forming a nitride layer on the thermal oxide layer, selectively etching the nitride layer to be removed over the device-isolating regions and selectively etching the thermal oxide layer and the semiconductor substrate with the patterned nitride layer serving as a mask to form trenches. The method further includes forming another thermal oxide layer on the surface of the trenches, forming an APCVD oxide layer on the entire surface including the thermal oxide layer and the patterned nitride layer, forming and annealing an HDPCVD oxide layer on the entire surface of the APCVD oxide layer to fill the trenches. The HDPCVD oxide layer is then polished using a CMP process. However, the HDPCVD oxide layer remains in the trenches.
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Dang Trung
LG Semicon Co. Ltd.
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