Method for forming dense multilevel interconnection metallurgy f

Details Method for forming dense multilevel interconnection metallurgy f Method for forming dense multilevel interconnection metallurgy f

1981-06-01

1984-01-03

Hearn, Brian E.

Metal working

Method of mechanical manufacture

Assembling or joining

29578, 148 15, 156653, 357 71, H01L 2104

Patent

active

044235470

ABSTRACT:
A method for providing high density multiple level metallurgy for integrated circuit devices in which a relatively thin layer of plasma produced silicon nitride is deposited over a first level of interconnection metallurgy formed on a layer of silicon oxide. Overlap via holes are etched in the nitride layer followed by deposition of a thicker layer of polyimide forming polymer. A second set of via holes larger than the first are provided in the polymer layer and a second layer of interconnection metallurgy is then deposited by a lift-off deposition technique.

REFERENCES:
patent: 3700497 (1972-10-01), Epifano et al.
patent: 3844831 (1974-10-01), Cass et al.
patent: 3846166 (1974-11-01), Saiki et al.
patent: 3936865 (1976-02-01), Robinson
patent: 4001870 (1977-01-01), Saiki et al.
Ryden et al., "A Metallization Providing Two Levels . . . Integrated Circuits," Tech. Dig. IEDM 1976, pp. 597-600 (12-6-76).
Aimi et al., "Solder Reflow Flip Chip Pad Transfers," IBM Tech. Discl. Bull., vol. 19, No. 3, p. 824 (8-76).
Heuber et al., "Self-Aligned Multiline Via Hole," IBM Tech. Discl. Bull., vol. 20, No. 9, pp. 3526-3527 (2-78).

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