Method for forming damascene metal gate

Details Method for forming damascene metal gate Method for forming damascene metal gate

2001-10-12

2003-12-16

Utech, Benjamin L. (Department: 1765)

Semiconductor device manufacturing: process

Chemical etching

Liquid phase etching

C438S750000, C438S751000, C438S754000

Reexamination Certificate

active

06664195

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method for forming highly integrated semiconductor devices and, more particularly, a method for forming damascene gate electrodes for highly integrated MOS transistors that includes effectively removing a dummy polysilicon layer.
2. Description of the Related Art
In general, a polysilicon gate electrode and a polycide gate electrode have been used as a gate electrode in sub-0.10 micron devices. However, polysilicon gate are associated with problems such as increases in the effective thickness of the gate insulating layer caused by gate depletion and threshold voltage variations resulting from dopant penetration from p
+
or n
+
polysilicon gate to a substrate and/or variations in dopant distribution. Further, it has proven difficult to produce consistent low-resistance conductors having extremely narrow line widths.
Therefore, metal gate electrodes are being developed as a substitute for the conventional polysilicon gate electrodes. Metal gate electrodes can solve the above-mentioned problems by eliminating the need for dopant in the manufacturing process. Metal gate electrodes, therefore, are able to provide threshold voltages that are symmetric between the NMOS and PMOS regions of a CMOS device by using metals that exhibit a work function located in a mid-band gap of silicon. Such metals include tungsten (W), tungsten nitride (WN), titanium (Ti), titanium nitride (TiN), molybdenum (Mo) and tantalum (Ta).
However, it has proven difficult to pattern metal gate electrodes. Also, during the subsequent ion implantation process necessary to form the source and drain regions, the surface of the metal film may be damaged. And similarly, the metal film may be subjected to thermal damage during the thermal process after ion implantation necessary to activate the dopants and/or anneal the crystal damage.
In order to solve these problems, a method has been proposed for forming a metal gate electrode using a damascene metal gate process. In the damascene metal gate process, a polysilicon gate is formed as a dummy gate and then source/drain regions are formed, thereby completing a transistor. The polysilicon gate is then removed and a metal gate is formed using a damascene process.
FIGS. 1A
to
1
F show a conventional method of forming a damascene metal gate.
Referring to
FIG. 1A
, a silicon oxide layer and a polysilicon layer are formed on a wafer (
10
), that is, a silicon substrate in a conventional method of forming polysilicon gate electrode and then, the layers are subjected to a patterning process, thereby forming a dummy gate insulating layer (
11
) and a dummy gate electrode (
12
).
Subsequently, source/drain regions (
13
) are formed by implanting ion impurities and spacers (
14
) are formed on the sidewalls of the dummy gate insulating layer (
11
) and the dummy gate electrode (
12
). Here, the source/drain regions may be formed using a LDD (Lightly Doped Drain) structure by the following steps. Firstly, a dummy gate electrode (
12
) is formed and then, source/drain regions are implanted with a low dopant concentration. Sidewall spacers (
14
) are then formed and the source/drain regions are implanted a high dopant concentration.
Referring to
FIG. 1B
, an interlayer insulating layer (
15
) is then formed over the resulting structure. The interlayer insulating layer (
15
) is then subjected to a chemical mechanical polishing (CMP) process as shown in
FIG. 1C
to remove a top portion of the interlayer insulating layer and expose the surfaces of dummy gate electrodes (
12
).
Referring to
FIG. 1D
, exposed dummy gate electrode (
12
) and dummy gate insulating layer (
11
) are selectively etched to expose the substrate (
10
). The removal of the dummy gate electrode (
12
) and the dummy gate insulating layer (
11
) produces a trench (
16
).
Referring to
FIG. 1E
, a thin insulating layer (
17
) and a metal layer (
18
), such as a tungsten layer, are formed on the interlayer insulating layer (
15
) trench (
16
). The interlayer insulating layer (
15
) is then exposed by CMP process, thereby forming a damascene gate insulating layer (
19
) and a damascene metal gate electrode (
20
).
The above-mentioned method of forming a damascene metal gate electrode provides certain advantages by deferring the gate electrode formation until after the transistor source/drain regions have been formed. For example, it is possible to avoid both plasma damage from the ion implantation processes and thermal damage that can occur during the follow-up thermal processes.
FIGS. 1A
to
1
D show process steps for selectively removing the polysilicon layer forming dummy gate (
12
). It is important to prevent damage of sidewall spacers (
14
) and the interlayer insulating layer (
15
) during the process of removing the polysilicon layer and it is particularly important to prevent damage to the exposed portion of the silicon substrate (
10
). Further, all residue from the polysilicon layer must be completely eliminated from the trench (
16
).
FIGS. 2A and 2B
show a conventional method of removing a dummy polysilicon layer for a dummy gate electrode.
FIG. 2A
shows a conventional method of removing a dummy polysilicon layer using a dry etch process and
FIG. 2B
shows a method using a wet etch process. In
FIG. 2A
, the dummy polysilicon layer is etched back and then removed using a plasma etch.
FIG. 2B
illustrates a method in which the dummy polysilicon layer is removed by a static etch process, that is, by dipping wafers (
22
) into a wet chemical etch bath (
21
) for a predetermined time.
However, these conventional methods of removing dummy polysilicon layers have certain problems.
First, plasma damage is caused on a wafer (
10
) when the trench (
16
of
FIG. 1D
) is formed by etching a dummy polysilicon layer. Further, a post-process treatment is required to remove polymers generated during the dry etch back process.
The wet etch process using the wet chemical is preferred to a dry etch process since it prevents plasma damage of substrate and it is an isotropic etch process. However, the wet etch process is advantageous only when the etch chemistry is such that the polysilicon layer is etched much more rapidly than the other layers that are exposed to the etch.
SUMMARY OF THE INVENTION
Therefore, the present invention has been made in order to solve the above-mentioned problems in the prior art. An object of the present invention is to provide a method for forming a damascene metal gate in which a dummy polysilicon layer is etched rapidly using a spin etch process.
In order to achieve the above object, the method for forming a damascene metal gate according to the present invention is characterized by the steps of: forming a dummy gate insulating layer and a polysilicon layer for a dummy gate on a wafer; forming an interlayer insulating layer on the wafer having the dummy polysilicon layer; polishing the interlayer insulating layer to expose a top of surface of the dummy polysilicon layer; and wet etching the exposed dummy polysilicon layer using a spin etch process.
According to the present invention, the dummy polysilicon layer is spin etched by providing wet chemicals to the surface of the dummy polysilicon layer while rotating the wafer.
Here, the speed of rotation of the wafer is 500 to 2000 rpm and a mixture of HF and HNO
3
is used as the wet chemical at a rate of 1:10 to 1:50 with the temperature of the wet etch chemical solution being between 20 and 100° C.


REFERENCES:
patent: 5869866 (1999-02-01), Fulford, Jr. et al.
patent: 5942449 (1999-08-01), Meikle
patent: 5960270 (1999-09-01), Misra et al.
Yagishita et al., “High Performance Damascene Metal Gate MOSFET's for 0.1 &mgr;m Regime”, IEEE Transactions on Electron Devices, vol. 47, No. 5, May 2000, pp. 1028-1034.
Yagishita et al., “High Performance Metal Gate MOSFET's Fabricated by CMP for 0.1 &mgr;m Regime”, IEEE IEDM 98—International Electron Devices Meeting, 1998, pp. 785-788.
Matsuki et al., “Cu/poly-Si Damascene Gate Stru

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