Semiconductor device manufacturing: process – Making device array and selectively interconnecting – Using structure alterable to nonconductive state
Reexamination Certificate
2006-12-12
2006-12-12
Whitehead, Jr., Carl (Department: 2813)
Semiconductor device manufacturing: process
Making device array and selectively interconnecting
Using structure alterable to nonconductive state
Reexamination Certificate
active
07148089
ABSTRACT:
An improved fuse link structure and method of forming the same, the method including forming a dual damascene structure by a trench-first process to form a dual damascene having a relatively thinner fuse link portion spanning an area between and overlying fuse metal interconnect structures including a mechanically robust dielectric insulating layer portion underlying the relatively thinner fuse link portion.
REFERENCES:
patent: 6376353 (2002-04-01), Zhou et al.
patent: 6562711 (2003-05-01), Powers
Hou Shang-Yong
Hung Meng-Chi
Tsai Hao-Yi
Harrison Monica D.
Taiwan Semiconductor Manufacturing Co. Ltd.
Tung & Associates
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